AD5231 datasheet(12/24 Pages) AD

12 / 24 page

REV. 0

AD5231

–12–

SDI Pin of the next package. Users may need to increase the clock

period because the pull-up resistor and the capacitive loading at

the SDO-SDI interface may require additional time delay between

subsequent packages. When two AD5231s are daisy-chained, 48

bits of data are required. The first 24 bits go to U2 and the second

24 bits go to U1. The 24 bits are formatted to contain the 4-bit

instruction, followed by the 4-bit address, 6-bit don’t care, then

the 10 bits of data. (The don’t care can be used to store user

information. See section Using Additional Internal Nonvolatile

EEMEM). The

CS should be kept low until all 48 bits are clocked

into their respective serial registers. The

CS is then pulled high to

complete the operation.

SDI

SDO

CLK

SDI

SDO

CLK

AD5231

Figure 5. Daisy Chain Configuration using SDO

Terminal Voltage Operation Range

The

AD5231 positive VDD and negative VSS power supply

defines the boundary conditions for proper 3 terminal digital

potentiometer operation. Supply signals present on terminals A,

B, and W that exceed VDD or VSS will be clamped by the internal

forward biased diodes (see Figure 6).

The ground pin of the AD5231 device is primarily used as a

digital ground reference, which needs to be tied to the PCB’s

common ground. The digital input control signals to the AD5231

must be referenced to the device ground pin (GND), and satisfy

the logic level defined in the specification table of this data

sheet. An internal level-shift circuit ensures that the common-

mode voltage range of the three terminals extends from VSS to

VDD, regardless of the digital input level.

VSS

VDD

Figure 6. Maximum Terminal Voltages Set by VDD and VSS

Power-Up Sequence

Sinc

e there are diodes to limit the voltage compliance at terminals

A, B, and W (see Figure 6), it is important to power VDD/VSS first

before applying any voltage to terminals A, B, and W. Otherwise,

the diode will be forward-biased such that VDD/VSS will be powered

unintentionally and may affect the rest of the user’s circuit. The

ideal power-up sequence is in the following order: GND, VDD, VSS,

Digital Inputs, and V A/B/W. The order of powering VA, VB, VW,

and digital inputs are not important as long as they are powered

after VDD/VSS.

Regardless of the power-up sequence and the ramp rates of the

power supplies, once VDD/VSS are powered, the power-on reset

remains effective, which retrieves EEMEM saved value to

RDAC register.

Latched Digital Outputs

A pair of digital outputs, O1 and O2, is available on the AD5231

that provide a nonvolatile logic 0 or logic 1 setting. O1 and O2 are

standard CMOS logic outputs (shown in Figure 7). These outputs

are ideal to replace functions often provided by DIP switches. In

addition, they can be used to drive other standard CMOS logic

controlled parts that need an occasional setting change.

VDD

GND

OUTPUTS

O1 AND O2

PINS

Figure 7. Logic Outputs O1 and O2

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