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AM29BDD160G датащи(PDF) 21 Page - Advanced Micro Devices |
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AM29BDD160G датащи(HTML) 21 Page - Advanced Micro Devices |
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21 / 80 page ![]() Am29BDD160G 19 Note: Operation is shown for the 32-bit data bus. For a 16-bit data bus, A-1 is required. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst, output on rising CLK edge, data hold for 1-CLK, IND/WAIT# as- serted on the last transfer before wrap-around. Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation Table 7. Valid Configuration Register Bit Definition for IND/WAIT# DOC WC CC Definition 0 0 1 IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge 0 1 1 IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge |
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