AD9783BCPZ datasheet(27/32 Pages) AD

27 / 32 page

Data Sheet

AD9780/AD9781/AD9783

Rev. C | Page 27 of 32

CH1 100mV

A CH1

58mV

125ps/DIV 2.12ns

20GSPS IT 2.5ps/PT

V1: 296mV

V2: –228mV

ΔV: –524mV

Figure 58. Eye Diagram of Data Source Used in Building the 500 MHz Timing

Data Array of Table 14

Over temperature, the valid sampling window shifts. Therefore,

when attempting operation of the device over 500 MHz, the

timing must be optimized again whenever the device undergoes

a temperature change of more than 20oC. Another consideration

in the timing of the digital data port is the propagation delay

variation from the clock output (DCOP/DCON) to the clock

input. If this varies significantly over time (more than 25% of

SET or HLD) due to temperature changes or other effects,

repeat this timing calibration procedure.

At sample rates of ≤400 MSPS, the interface timing margin is

sufficient to allow for a simplified procedure. In this case, the

SEEK bit can be recorded as SMP is swept through the range

from 0 to 31. The center of the first valid sampling window can

then be chosen as the optimal value of SMP. Using the 400 MHz

case from Table 14 as an example, the first valid sampling

window occurs for SMP values of 7 to 13. The center of this

window is 10, so 10 can be used as the optimal SMP value.

BIST OPERATION

The BIST feature in the AD9780/AD9781/AD9783 is a simple

type adder and is a user synchronizable BIST feature. In

while writing zeros to the data bits for at least eight clock cycles

to propagate to the BIST signature module. Then enable BIST

by writing 0x80 to Register 0x1A. Next, begin writing a known

set of vectors to the data inputs. Proceed by writing zeros into

the bits after the vectors while the BIST read is being performed.

Perform a BIST read by writing 0xC0 to Register 0x1A to

receive the unique sum of rising edge data in Register 0x1B

and Register 0x1C and a unique sum of falling edge data in

always give the same values for the same vectors

each time they are sent.

DRIVING THE CLK INPUT

The CLK input requires a low jitter differential drive signal. It is

a PMOS input differential pair powered from the 1.8 V supply;

therefore, it is important to maintain the specified 400 mV

input common-mode voltage. Each input pin can safely swing

from 200 mV p-p to 1 V p-p about the 400 mV common-mode

voltage. CLK can be driven by an offset ac-coupled signal, as

shown in Figure 59.

P_IN

CLKP

50Ω

0.1µF

N_IN

CLKN

VCM = 400mV

Figure 59. DAC CLK Drive Circuit

If a clean sine clock is available, it can be transformer-coupled

to CLKP and CLKN as shown in Figure 60. Use of a CMOS or

TTL clock is also acceptable for lower sample rates. It can then

be ac-coupled, as described in this section. Alternatively, it can

be transformer-coupled and clamped, as shown in Figure 60.

50Ω

TTL OR CMOS

CLK INPUT

CLKP

CLKN

VCM = 400mV

BAV99ZXCT

HIGH SPEED

DUAL DIODE

0.1µF

Figure 60. TTL or CMOS DAC CLK Drive Circuit

A simple bias network for generating the 400 mV common-

mode voltage is shown in Figure 61. It is important to use

CVDD18 and CGND for the clock bias circuit. Any noise or

other signal coupled onto the clock is multiplied by the DAC

digital input signal and can degrade the DAC’s performance.

0.1µF

1nF

VCM = 400mV

CVDD18

CGND

1kΩ

287Ω

1nF

Figure 61. DAC CLK VCM Generator Circuit

AD9783BCPZ датащи(PDF) 27 Page - Analog Devices

AD9783BCPZ датащи(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL