AD9783BCPZ datasheet(28/32 Pages) AD

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AD9780/AD9781/AD9783

Data Sheet

Rev. C | Page 28 of 32

FULL-SCALE CURRENT GENERATION

Internal Reference

Full-scale current on the I DAC and Q DAC can be set from

8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is

used to set up a current in an external resistor connected to

FS ADJ (Pin 54). A simplified block diagram of the reference

circuitry is shown in Figure 62. The recommended value for

the external resistor is 10 kΩ, which sets up an IREFERENCE in the

resistor of 120 μA, which in turn provides a DAC output full-

scale current of 20 mA. Because the gain error is a linear function

of this resistor, a high precision resistor improves gain matching

to the internal matching specification of the devices. Internal

current mirrors provide a current-gain scaling, where I DAC or

Q DAC gain is a 10-bit word in the SPI port register. The default

value for the DAC gain registers gives a full-scale current output

(IFS) of approximately 20 mA, where IFS is equal to

IFS = (86.6 + (0.220 × DAC gain)) × 1000/R

CURRENT

SCALING

1.2V BAND GAP

I DAC GAIN

Q DAC GAIN

AD9783

I DAC

Q DAC

DAC FULL-SCALE

REFERENCE CURRENT

REFIO

FS ADJ

0.1µF

10kΩ

Figure 62. Reference Circuitry

256

512

768

1024

DAC GAIN CODE

Figure 63. IFS vs. DAC Gain Code

DAC TRANSFER FUNCTION

Each DAC output of the AD9780/AD9781/AD9783 drives two

complementary current outputs, IOUTP and IOUTN. IOUTP provides

a near IFS when all bits are high. For example,

DAC CODE = 2N − 1

where N = 12/14/16 bits for AD9780/AD9781/AD9783

(respectively), while IOUTN provides no current.

The current output appearing at IOUTP and IOUTN is a function of

both the input code, and IFS and can be expressed as

IOUTP = (DAC DATA/2N) × IFS

(1)

IOUTN = ((2N − 1) − DAC DATA)/2N × IFS

(2)

where DAC DATA = 0 to 2N − 1 (decimal representation).

The two current outputs typically drive a resistive load directly

or via a transformer. If dc coupling is required, IOUTP and IOUTN

must be connected to matching resistive loads (RLOAD) that are tied

to analog common (AVSS). The single-ended voltage output

appearing at the IOUTP and IOUTN pins is

VOUTP = IOUTP × RLOAD

(3)

VOUTN = IOUTN × RLOAD

(4)

Note that to achieve the maximum output compliance of 1 V at

the nominal 20 mA output current, RLOAD must be set to 50 Ω.

Also note that the full-scale value of VOUTP and VOUTN must not

exceed the specified output compliance range to maintain

specified distortion and linearity performance.

There are two distinct advantages to operating the AD9780/

AD9781/AD9783 differentially. First, differential operation

helps cancel common-mode error sources associated with IOUTP

and IOUTN, such as noise, distortion, and dc offsets. Second, the

differential code-dependent current and subsequent output

voltage (VDIFF) is twice the value of the single-ended voltage

output (VOUTP or VOUTN), providing 2× signal power to the load.

VDIFF = (IOUTP – IOUTN) × RLOAD

(5)

ANALOG MODES OF OPERATION

The AD9780/AD9781/AD9783 use a proprietary quad-switch

architecture that lowers the distortion of the DAC by eliminating a

code-dependent glitch that occurs with conventional dual-switch

architectures. This architecture eliminates the code-dependent

glitches, but creates a constant glitch at a rate of 2 × fDAC. For

communications systems and other applications requiring good

frequency domain performance from the DAC, this is seldom

problematic.

The quad-switch architecture also supports two additional

modes of operation: mix mode and return-to-zero mode. The

waveforms of these two modes are shown in Figure 64. In mix

mode, the output is inverted every other half clock cycle. This

effectively chops the DAC output at the sample rate. This chop-

ping has the effect of frequency shifting the sinc roll-off from dc

to fDAC. Additionally, there is a second subtle effect on the output

spectrum. The shifted spectrum is also shaped by a second sinc

function with a first null at 2 × fDAC. The reason for this shaping

is that the data is not continuously varying at twice the clock

rate, but is simply repeated.

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