MBM29PL64LM datasheet(34/69 Pages) SPANSION

34 / 69 page

MBM29PL64LM90/10

Word/Byte Configuration

BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the

device operates in the word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven

low, the device operates in byte (8-bit) mode. In this mode, DQ15/A-1 pin becomes the lowest address bit, and

DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence com-

mands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.

Data Protection

The device is designed to offer protection against accidental erasure or programming caused by spurious system

level signals that may exist during power transitions. During power up the device automatically reset the internal

state machine in Read mode. Also, with its control register architecture, alteration of memory contents only

occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up

and power-down transitions or system noise.

(1) Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.

Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level

is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent

unintentional writes when VCC is above VLKO.

If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.

(2) Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

(3) Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must

be a logical zero while OE is a logical one.

(4) Power-up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to read mode on power-up.

(5) Sector Protection

Device user is able to protect each sector group individually to store and protect data. Protection circuit voids

both write and erase commands that are addressed to protected sectors.

Any commands to write or erase addressed to protected sector are ignored .

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