MBM29PL64LM datasheet(31/69 Pages) SPANSION

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MBM29PL64LM90/10

DQ7

Data Polling

The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in

progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce

reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the

device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the

device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to

read device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in “Data Polling

Algorithm” in sFLOW CHART.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector addresses of sectors being erased, not protected

sectors. Otherwise, the status may become invalid.

If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1

µs, then

the device returns to read mode. After an erase command sequence is written, if all sectors selected for erasing

are protected, Data Polling on DQ7 is active for approximately 100

µs, then the device returns to read mode. If

not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected.

Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change

asynchronously while the output enable (OE) is asserted low. This means that the device is driving status

information on DQ7 at one instant of time, and then that byte’s valid data the next. Depending on when the system

samples the DQ7 output, it may read the status or valid data. Even if the device completes the Embedded

Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may still be invalid. The valid data

on DQ7 to DQ0 will be read on the successive read attempts.

The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-

rithm, Erace Suspendmode or sector erase time-out.

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in sTIMING DIAGRAM for the Data

Polling timing specifications and diagram.

DQ6

Toggle Bit I

The device also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms

are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data

from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase

Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts.

During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse

sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse

in the six write pulse sequences. The Toggle Bit I is active during the sector time out.

In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1

µs and

then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for

the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 100

µs and

then drop back into read mode, having data kept remained.

Either CE or OE toggling will cause the DQ6 to toggle. See “Toggle Bit l Timing Diagramduring Embedded

Algorithm Operations” in sTIMING DIAGRAM for the Toggle Bit I timing specifications and diagram.

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