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Data Sheet

AD5293

Rev. E | Page 19 of 24

RESET

A low-to-high transition of the hardware RESET pin loads the

RDAC register with midscale. The AD5293 can also be reset

through software by executing Command 3 (see Table 11).

The control register is restored with default bits (see Table 13).

RESISTOR PERFORMANCE MODE

This mode activates a new, patented 1% end-to-end resistor

tolerance that ensures a ±1% resistor tolerance on each code,

that is, code = half scale, RWB =10 kΩ ± 100 Ω. See Table 2 and

Table 4 to verify which codes achieve ±1% resistor tolerance.

The resistor performance mode is activated by programming

Bit C2 of the control register (see Table 12 and Table 13). The

typical settling time is shown in Figure 32.

SDO PIN AND DAISY-CHAIN OPERATION

The serial data output pin (SDO) serves two purposes: it can

be used to read the contents of the wiper setting and control

Table 11) or the SDO pin can be used in daisy-chain mode.

Data is clocked out of SDO on the rising edge of SCLK. The

SDO pin contains an open-drain N-channel FET that requires

a pull-up resistor if this pin is used. To place the pin in high

impedance and minimize the power dissipation when the pin

is used, the 0x8001 data word followed by Command 0 should

be sent to the part. Table 10 provides a sample listing for the

sequence of the serial data input (DIN). Daisy chaining mini-

mizes the number of port pins required from the controlling IC.

As shown in Figure 45, users need to tie the SDO pin of one

package to the DIN pin of the next package. Users may need to

increase the clock period, because the pull-up resistor and the

capacitive loading at the SDO-to-DIN interface may require

additional time delay between subsequent devices.

When two AD5293s are daisy-chained, 32 bits of data are required.

The first 16 bits go to U2, and the second 16 bits go to U1. The

SYNC pin should be held low until all 32 bits are clocked into

their respective serial registers. The SYNC pin is then pulled

high to complete the operation.

Keep the SYNC pin low until all 32 bits are clocked into their

respective serial registers. The SYNC pin is then pulled high to

complete the operation.

DIN

SDO

SCLK

2.2kΩ

DIN

SDO

AD5293

SYNC

VLOGIC

MICRO-

CONTROLLER

SCLK

MOSI

SYNC

Figure 45. Daisy-Chain Configuration Using SDO

Table 10. Minimize Power Dissipation at the SDO Pin

DIN

SDO1

Action

0xXXXX

Last user command sent to the digital potentiometer

0x8001

0xXXXX

Prepares the SDO pin to be placed in high impedance mode

0x0000

High impedance

The SDO pin is placed in high impedance

X = don’t care.

Table 11. Command Operation Truth Table

Command

Command Bits[B13:B10]

Data Bits[B9:B0]1

Operation

NOP command. Do nothing.

Write contents of serial register data

to RDAC.

Read RDAC wiper setting from SDO

output in the next frame.

Reset. Refresh RDAC with midscale code.

Write contents of serial register data

to control register.

Read control register from SDO output

in the next frame.

Software power-down.

D0 = 0 (normal mode).

D0 = 1 (device placed in shutdown

mode).

X = don’t care.

Table 12. Control Register Bit Map

X = don’t care.

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