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GMS77C1001 датащи(PDF) 28 Page - Hynix Semiconductor |
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GMS77C1001 датащи(HTML) 28 Page - Hynix Semiconductor |
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28 / 44 page ![]() GMS77C1000/GMS77C1001 July. 2001 Ver. 1.1 25 11. TIMER0 MODULE AND TMR0 REGISTER The Timer0 module has the following features: • 8-bit timer/counter register, TMR0 • 8-bit software programmable prescaler • Internal or external clock select • Edge select for external clock Figure 11-1 is a simplified block diagram of the Timer0 module, while Figure 11-2 shows the electrical structure of the Timer0 input. FIGURE 11-1 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FIGURE 11-2 ELECTRICAL STRUCTURE OF EC0 PIN TCY ( = FOSC/4) 1 8-bit Prescaler EC0 pin 0 Sync with Internal Clocks TMR0 reg 8 Data bus (2cycle delay) T0SE 8 T0CS MUX 0 1 MUX 1 0 PSA MUX 8 - to - 1 MUX Watchdog Timer MUX PS2:PS0 PSA PSA 1 0 WDT Time-Out WDT Enable bit clear ECO P N pin RIN Schmitt Trigger Input Buffer (1) Note 1: ESD protection circuits Noise Filter |
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