8431AM-21

www.icst.com/products/hiperclocks.html

REV. A APRIL 27, 2005

8

Integrated

Circuit

Systems, Inc.

ICS8431-21

TO

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8431-21 provides

separate power supplies to isolate any high switching noise

from the outputs to the internal PLL. V

be individually connected to the power supply plane through

vias, and bypass capacitors should be used for each pin. To

achieve optimum jitter performance, better power supply iso-

lation is required.

Figure 3 illustrates how a 10

Ω along with a

10

μF and a .01μF bypass capacitor should be connected to

each V

10

Ω

V

CCA

10

μF

.01

μF

3.3V

.01

μF

V

CC

The clock layout topology shown below is typical for

IA64/32 platforms. The two different layouts mentioned are

recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

drive 50

Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion.

Figures 2A and 2B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN