8431AM-21

www.icst.com/products/hiperclocks.html

REV. A APRIL 27, 2005

2

Integrated

Circuit

Systems, Inc.

ICS8431-21

TO

The PLL loop divider or M divider is programmed by using

inputs M0 through M8. While the nP_LOAD input is held LOW,

the data present at M0:M8 is transparent to the M divider. On

the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is

latched into the M divider and any further changes at the

M0:M8 inputs will not be seen by the M divider until the next

LOW transition on nP_LOAD.

The relationship between the VCO frequency, the crystal fre-

quency and the M divider is defined as follows:

The M value and the required values of M0:M8 for programming

the VCO are shown in

Table 3B, Programmable VCO Frequency

Function Table. The frequency out is defined as follows:

For the ICS8431-21, the output divider may be set to either

÷2

or

÷4 by the DIV_SEL pin. For an input of 16 MHz, valid

M values for which the PLL will achieve lock are defined as:

250

≤ M ≤ 511.

The ICS8431-21 features a fully integrated PLL and therefore

requires no external components for setting the loop bandwidth.

The output of the oscillator is divided by 16 prior to the phase

detector. With a 16MHz crystal this provides a 1MHz reference

frequency.The VCO of the PLL operates over a range of 250MHz

to 700MHz.The output of the M divider is also applied to the phase

detector.

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjusting

the VCO control voltage. Note that for some values of M (ei-

ther too high or too low), the PLL will not achieve lock. The

output of the VCO is scaled by a divider prior to being sent to

the LVPECL output buffer. The divider provides a 50% output

duty cycle.

The programmable features of the ICS8431-21 support four

output operational modes and a programmable M divider and

output divider. The four output operational modes are spread

spectrum clocking (SSC), non-spread spectrum clock and

two test modes and are controlled by the SSC_CTL[1:0] pins.

16

M

fVCO =

fxtal x

N

FOUT =

fVCO

=

16 x N

fxtal x M