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Data Sheet

AD9554

Rev. D | Page 17 of 116

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUT3B

VDD

OUT3A

VDD

REFD

VDD

REFA

VDD

OUT0A

VDD

OUT0B

OUT2B

VDD

OUT2A

VDD

REFC

VDD

REFB

VDD

OUT1A

VDD

OUT1B

PIN 1

INDICATOR

AD9554

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP.

IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO

ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE,

AND MECHANICAL STRENGTH BENEFITS.

Figure 2. Pin Configuration

Table 20. Pin Function Descriptions

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

OUT3B

HCSL, LVDS-

compatible,

LVPECL-

Compatible

PLL3 Complementary Output 3B. Complementary signal to the output provided

on Pin 72 (OUT3B).

2, 5, 9, 10, 14,

17, 20, 21, 25,

34, 35, 38, 41,

45, 46, 50, 53,

56, 57, 62, 70,

VDD

Power

1.5 V or 1.8 V Power Supply. See the Power Supply Partitions section for

information about the recommended grouping of the power supply pins.

OUT3A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL3 Output 3A. This HCSL output can be configured as a LVDS- or LVPECL-

compatible output. LVPECL and LVDS levels can be achieved by ac coupling

and using the Thevenin equivalent termination as described in the

Input/Output Termination Recommendations section.

OUT3A

HCSL, LVDS-

compatible,

LVPECL-

compatible

PLL3 Complementary Output 3A. Complementary signal to the output

provided on Pin 3 (OUT3A).

6, 13, 42, 49

M3, M0, M1,

I/O

1.5 V/1.8 V

CMOS

Configurable Input/Output Pins. These pins are used for status and control of

the AD9554. These pins are also used at power-up and reset to control the

optional external EEPROM. See the Multifunction Pins at Reset/Power-Up

section for more information about the internal 100 kΩ pull-up or pull-down

resistors. These pins are on the VDD power domain (Pin 9, Pin 10, Pin 45, and

Pin 46), and the logic high voltage for this pin matches the voltage of the VDD

pins.

REFD

Differential

input

Reference D Input. This internally biased input is typically ac-coupled; when

configured in this manner, it can accept any differential signal with single-

ended swing up to the VDD power supply. If dc-coupled, the input can be

LVDS or single-ended CMOS provided that VIH ≤ VDD.

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