AD9554 datasheet(39/116 Pages) AD

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Data Sheet

AD9554

Rev. D | Page 39 of 116

SYSTEM CLOCK (SYSCLK)

SYSCLK INPUTS

Functional Description

The SYSCLK circuit provides a low jitter, stable, high frequency

clock for use by the rest of the chip. The XOA and XOB pins

connect to the internal SYSCLK multiplier. The SYSCLK multiplier

can synthesize the system clock by connecting a crystal resonator

across the XOA and XOB input pins or by connecting a low

frequency clock source. The optimal signal for the system clock

input is either a crystal in the 50 MHz range or an ac-coupled

square wave with 800 mV p-p amplitude.

SYSCLK Reference Frequency

For the AD9554 to function properly, enter the system clock

reference frequency into Register 0x0202 to Register 0x0205.

The ability of the AD9554 to accurately measure the frequency

of the reference input depends on how accurately this register

setting matches the frequency on the system clock input.

Choosing the SYSCLK Source

There are two internal paths for the SYSCLK input signal:

crystal resonator (XTAL) and nonXTAL.

Using a TCXO for the system clock is a common use for the

nonXTAL path. Applications requiring DPLL loop bandwidths

of less than 50 Hz or high stability in holdover mode require a

TCXO or oven controlled crystal oscillator (OCXO). As an

alternative to the 49.152 MHz crystal for these applications, the

AD9554 reference design uses a 19.2 MHz TCXO, which offers

excellent holdover stability and a good combination of low jitter

and low spurious content.

The differential receiver connected to the XOA and XOB pins is

self-biased to a dc level of ~0.6 V, and ac coupling is strongly

recommended to maintain a 50% input duty cycle. When a 3.3 V

CMOS oscillator is in use, it is important to ac-couple and use a

voltage divider to reduce the input high voltage to a maximum

of 1.14 V. The target voltage swing is 800 mV p-p. See Figure 25

for details on connecting a 3.3 V CMOS TCXO to the system

clock input.

The nonXTAL input path permits the user to provide an

LVPECL, LVDS, CMOS, or sinusoidal low frequency clock for

multiplication by the integrated SYSCLK PLL. However, when

using a sinusoidal input signal, it is best to use a frequency of

≥20 MHz. Otherwise, the resulting low slew rate can lead to poor

noise performance. Note that there is an optional 2× frequency

multiplier to double the rate at the input to the SYSCLK PLL and

potentially reduce the PLL in-band noise. However, to avoid

exceeding the maximum PFD rate of 300 MHz, the 2× frequency

multiplier is only for input frequencies less than 150 MHz. Note

that using the doubler when the duty is not close to 50% results

in higher spurious noise and may prevent the system clock PLL

from locking.

The nonXTAL path also includes an input divider (M) that is

programmable for divide-by-1, -2, -4, or -8. The purpose of the

divider is to allow additional flexibility in setting the system

clock frequency to avoid spurs in the output clocks.

The XTAL path enables the connection of a crystal resonator

(typically 12 MHz to 50 MHz) across the XOA and XOB pins.

An internal amplifier provides the negative resistance required

to induce oscillation. The internal amplifier expects an AT cut,

fundamental mode crystal with a 100 Ω maximum motional

resistance. The following crystals, listed in alphabetical order,

may meet these criteria. Analog Devices does not guarantee

their operation with the AD9554, nor does Analog Devices

endorse one crystal supplier over another. The AD9554

reference design uses a 49.152 MHz crystal, which is high

performance, low spurious content, and readily available.



AVX/Kyocera CX3225SB



ECS, Inc. ECX-32



Epson/Toyocom TSX-3225



Fox FX3225BS



NDK NX3225SA



Siward SX-3225



Suntsu SCM10B48-49.152 MHz

SYSCLK MULTIPLIER

The SYSCLK PLL multiplier is an integer-N design with an

integrated VCO. It provides a means to convert a low frequency

clock input to the desired system clock frequency, fSYS (2250 MHz

to 2415 MHz). The SYSCLK PLL multiplier accepts input signals of

between 10 MHz and 268 MHz. The PLL contains a feedback

divider (K) that is programmable for divide values between 4

and 255.

fSYS = fOSC ×

JDIV

SYSCLK

KDIV

SYSCLK

where:

fOSC is the frequency at the XOA and XOB pins.

SYSCLK_KDIV is the K divider value stored in Register 0x0200.

SYSCLK_JDIV is the system clock J1 divider that is determined

by setting Register 0x0201[2:1].

If the system clock doubler is used, the value of SYSCLK_KDIV

must be half of its original value.

The system clock multiplier features a simple lock detector that

compares the time difference between the reference and

feedback edges. The most common cause of the SYSCLK

multiplier not locking is a non-50% duty cycle at the SYSCLK

input while the system clock doubler is enabled.

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