AD9554 datasheet(32/116 Pages) AD

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AD9554

Data Sheet

Rev. D | Page 32 of 116

PLL_0 Through PLL_3 Operational Controls

The PLL_0 through PLL_3 operational controls are located at



APLL calibration and synchronization



Output driver enable and power-down



DPLL reference input switching modes



DPLL open-loop phase stepping control

The user free run bits that enable user free run mode reside in

the following registers:



APLL VCO Calibration

VCO calibration ensures that the VCO has sufficient operating

margin to function across the full temperature range. The user

can calibrate each of the four VCOs independently of one

another. When calibrating the APLL VCO, it is important to

remember the following conditions:



The APLL VCO calibration does not occur until the system

clock is stable.



The APLL VCO must have the correct frequency from the

30-bit digitally controlled oscillator (DCO) during

calibration. The free running tuning word is found in



The APLL VCO must be recalibrated any time the APLL

frequency changes.



APLL VCO calibration occurs on the low to high transition

of the APLL VCO calibration bit (Register 0x0A20[1] for

APLL_0, Register 0x0A40[1] for APLL_1, Register 0x0A60[1]

for APLL_2, and Register 0x0A80[1] for APLL_3).



The VCO calibration bit is not an autoclearing bit.

Therefore, this bit must be cleared (and an IO_UPDATE

issued) before the APLL is recalibrated.



The best way to monitor successful APLL calibration is by

monitoring the APLL locked bit in the following registers:

APLL_1, Register 0x0D60[3] for APLL_2, and

Generate the Output Clock

If Register 0x0435 (for PLL_0), Register 0x0535 (for PLL_1),

programmed for automatic clock distribution synchronization

via the DPLL phase or frequency lock, the synthesized output

signal appears at the clock distribution outputs. Otherwise, set and

then clear the soft sync bit (Bit 2 in Register 0x0A20 for APLL_0,

Bit 2 in Register 0x0A40 for APLL_1, Bit 2 in Register 0x0A60

for APLL_2, and Bit 2 in Register 0x0A80 for APLL_3) or use a

multifunction pin input (if programmed accordingly) to generate a

clock distribution sync pulse. This sync pulse causes the

synthesized output signal to appear at the clock distribution

outputs. Note that the sync pulse is delayed until the APLL

achieves lock following APLL calibration.

Generate the Reference Acquisition

After the registers are programmed, the DPLLs lock to the

reference input that has been manually selected (if any), or the

first available reference that has the highest priority.

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