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AD9543BCPZ датащи(PDF) 14 Page - Analog Devices

номер детали AD9543BCPZ
подробное описание детали  Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner
PDF  66 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9543BCPZ датащи(HTML) 14 Page - Analog Devices

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AD9543
Data Sheet
Rev. 0 | Page 14 of 66
SERIAL PORT SPECIFICATIONS
Serial Port Interface (SPI) Mode
Table 18.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CSB
Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V
Input Logic 1 Voltage
VDDIOA − 0.4
V
Input Logic 0 Voltage
0.4
V
Input Logic 1 Current
1
µA
Input Logic 0 Current
1
µA
SCLK
Input Logic 1 Voltage
VDDIOA − 0.4
V
Input Logic 0 Voltage
0.4
V
Input Logic 1 Current
1
µA
Input Logic 0 Current
1
µA
SDIO
As an Input
Input Logic 1 Voltage
VDDIOA − 0.4
V
Input Logic 0 Voltage
0.4
V
Input Logic 1 Current
1
µA
Input Logic 0 Current
1
µA
As an Output
Output Logic 1 Voltage
VDDIOA − 0.2
V
1 mA load current
Output Logic 0 Voltage
0.2
V
1 mA load current
SDO
Output Logic 1 Voltage
VDDIOA − 0.2
V
1 mA load current
Output Logic 0 Voltage
0.2
V
1 mA load current
Leakage Current
±1
µA
SDO inactive (high impedance)
TIMING
Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V
SCLK
Clock Rate, 1/tCLK
50
MHz
Pulse Width High, tHIGH
5
ns
Pulse Width Low, tLOW
9
ns
SDIO to SCLK Setup, tDS
2.2
ns
SCLK to SDIO Hold, tDH
0
ns
SCLK to Valid SDIO and SDO, tDV
9
ns
CSB to SCLK Setup, tS
1.5
ns
CSB to SCLK Hold, tC
0
ns
CSB Minimum Pulse Width High
1
tCLK



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