AD9543BCPZ datasheet(58/66 Pages) AD

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AD9543

Data Sheet

Rev. 0 | Page 58 of 66

Note that the condition map allows multiple conditions to

exist at any given moment. This multiconditional processing

mechanism enables the user to have one download instruction

sequence with many possible outcomes, depending on the

value of the condition ID and the order in which the controller

encounters conditional instructions. An example of the use of

conditional processing is shown in Table 33.

Table 33. Example Conditional Processing Sequence

Instruction

Operation

0x00 to 0x7F

A sequence of register transfer instructions

that execute unconditionally

0xB1

Apply Condition 1

0x00 to 0x7F

A sequence of register transfer instructions

that execute only if the condition ID is 1

0xB2

Apply Condition 2

0xB3

Apply Condition 3

0x00 to 0x7F

A sequence of register transfer instructions that

execute only if the condition ID is 1, 2, or 3

0x91

Calibrate the system clock PLL

0xB0

Clear condition map

0x80

Input/output update

0xFF

Terminate sequence

Pause Instruction (0xFE)

The EEPROM controller only recognizes the pause instruction

during an upload sequence. Upon encountering a pause

instruction, the EEPROM controller enters an idle state, but

preserves the current value of the EEPROM address pointer.

One use of the pause instruction is for saving multiple, yet

distinct, values of the same AD9543 register, which is useful for

sequencing power-up conditions.

The pause instruction is also useful for executing an upload

sequence requiring more space than is available in the EEPROM

sequence registers in the EEPROM section of the register map

(see the EEPROM Upload section).

End of Data Instruction (0xFF)

When the EEPROM controller encounters an end of data

instruction during an upload sequence, it stores the instruction

in EEPROM along with the computed checksum, clears the

EEPROM address pointer, and then enters an idle state. When

encountered during a download sequence, however, the

EEPROM controller clears the EEPROM address pointer,

verifies the checksum, and then enters an idle state.

Note that during EEPROM downloads, condition instructions

always execute unconditionally.

MULTIDEVICE SUPPORT

Multidevice support enables multiple AD9543 devices to share

the contents of a single EEPROM. There are two levels of multi-

device support. Level 1 supports a configuration where multiple

AD9543 devices share a single EEPROM through a dedicated

I2C bus. Level 2 supports a configuration where multiple AD9543

devices share a single EEPROM connected to a common I2C bus

that includes other I2C master devices. Figure 52 and Figure 53

show the Level 1 and Level 2 configurations, respectively.

SDA

SCL

CPU

EEPROM

SCL SDA

SCL

SDA

SCL SDA

AD9543

DEVICE 1

SCL SDA

AD9543

DEVICE 2

SCL SDA

Figure 52. Level 1 Multidevice Configuration

AD9543

DEVICE 1

SCL SDA

AD9543

DEVICE 2

SCL SDA

SDA

SCL

CPU

SDA

SCL

EEPROM

SCL

SDA

Figure 53. Level 2 Multidevice Configuration

Multidevice Bus Arbitration

The EEPROM controller implements bus arbitration by

continuously monitoring the SDA and SCL bus signals for start

and stop conditions. The controller can determine whether the

bus is idle or busy. If the bus is busy, the EEPROM controller

delays its pending I2C transfer until a stop condition indicates

that the bus is available.

Bus arbitration is essential in cases where two I2C master devices

simultaneously attempt an I2C transfer. For example, if one I2C

master detects that SDA is Logic 0 when it is intended to be Logic 1,

it assumes that another I2C master is active and immediately

terminates its own attempt to transfer data. Similarly, if one I2C

master detects that SCL is Logic 0 prior to entering a start state,

it assumes that another I2C master is active and stalls its own

attempt to drive the bus.

In either case, the prevailing I2C master completes its current

transaction before releasing the bus. Because the postponed I2C

master continuously monitors the bus for a stop condition, it

attempts to seize the bus and carry out the postponed transaction

on detection of such a stop condition.

The EEPROM controller includes an arbitration timer to optimize

the bus arbitration process. Specifically, when the EEPROM

controller postpones an I2C transfer as a result of detecting bus

contention, it starts the arbitration timer. If the EEPROM controller

fails to detect a stop condition within 255 SCL cycles, it attempts

to force another transaction. If the bus is still busy, the EEPROM

controller restarts the arbitration timer, and the process continues

until the EEPROM controller eventually completes the pending

transaction.

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