AD9542 datasheet(29/61 Pages) AD

29 / 61 page

Data Sheet

AD9542

Rev. 0 | Page 29 of 61

SYSTEM CLOCK PLL

Note that throughout the System Clock PLL section, unless

otherwise specified, any referenced bits, registers, or bit fields

reside in the system clock (SYSCLK) section of the register map

(Register 0x0200 to Register 0x0209).

The system clock PLL (see Figure 39) comprises an integer-N

frequency synthesizer with a fully integrated loop filter and voltage

controlled oscillator (VCO). The VCO output is the AD9542

system clock with a frequency range of 2250 MHz to 2415 MHz.

The XOA and XOB pins constitute the input to the system clock

PLL to which a user connects a clock source or crystal resonator.

VCO

CALIBRATION

LOCK

DETECTOR

SYSTEM

CLOCK

XOA

XTAL

DIRECT

2250MHz TO

2415MHz

XOB

2×

÷J

÷K

1, 2, 4, 8

4 TO 255

PFD,

CHARGE PUMP,

LOOP FILTER

AD9542

Figure 39. System Clock PLL Block Diagram

SYSTEM CLOCK INPUT FREQUENCY

DECLARATION

Proper operation of the AD9542 requires the user to declare

the input reference frequency to the system clock PLL. To do

so, program the SYSCLK reference frequency bit field, which

constitutes the nominal frequency of the system clock PLL

input reference. The AD9542 evaluation software frequency

planning wizard calculates this value for the user.

SYSTEM CLOCK SOURCE

The XOA and XOB pins serve as the input connection to the

system clock PLL, giving the user access to a crystal path or a

direct path. Path selection is via the enable maintaining

amplifier bit, where a Logic 0 (default) selects the direct path

and Logic 1 selects the crystal path. The optimal reference

source for the system clock input is a crystal resonator in the

50 MHz range or an ac-coupled square wave source (single-

ended or differential) with 800 mV p-p amplitude.

Crystal Path

The crystal path supports crystal resonators in the 25 MHz to

60 MHz frequency range. An internal maintaining amplifier

provides the negative resistance required to induce oscillation. The

internal amplifier expects an AT cut, fundamental mode crystal

with a maximum motional resistance of 100 Ω for crystals up to

52 MHz, and 50 Ω for crystals up to 60 MHz. The following

crystals, listed in alphabetical order, may meet these criteria.

•

AVX/Kyocera CX3225SB

•

ECS, Inc. ECX-32

•

Epson/Toyocom TSX-3225

•

Fox FX3225BS

•

NDK NX3225SA

•

Siward SX-3225

•

Suntsu SCM10B48-49.152 MHz

Analog Devices, Inc., does not guarantee the operation of the

AD9542 with the aforementioned crystals, nor does Analog

Devices endorse one crystal supplier over another. The AD9542

reference design uses a readily available high performance

49.152 MHz crystal with low spurious content.

Direct Path

The direct path has a differential receiver with a self bias of

0.6 V dc. Generally, the presence of the bias voltage necessitates

the use of ac coupling between the external source and the XOA

and XOB pins. Furthermore, when using a 3.3 V CMOS oscillator

as the system clock PLL reference source, in addition to ac

coupling, it is important to use a voltage divider to reduce the

3.3 V swing to a maximum of 1.14 V (note that the optimal

voltage swing is 800 mV p-p). The external signal must exhibit a

50% duty cycle for best performance.

The direct path supports low frequency LVPECL, LVDS,

CMOS, or sinusoidal clock sources as a reference to the system

clock PLL. For a sinusoidal source, however, it is best to use a

frequency of 50 MHz or greater. The low slew rate of lower

frequency sinusoids tends to yield nonoptimal noise performance.

Applications requiring low DPLL loop bandwidth require the

improved stability provided by a TCXO or OCXO. Loop

bandwidths below approximately 50 Hz may prevent the PLL

from locking or cause random loss of lock events when using a

less stable PLL reference source.

Although one method to mitigate this problem is to use a high

stability system clock source (like an OCXO), the AD9542

provides integrated system clock compensation capability,

which lessens the stability requirement on the system clock

while providing the outstanding phase noise of the higher

frequency crystal. To use this feature, connect a 40 MHz to

60 MHz crystal to the XOA/XOB pins (as in Figure 23), and

connect either a TCXO or OCXO to either an unused reference

input or an Mx pin (as shown in Figure 24).

2× FREQUENCY MULTIPLIER

The system clock PLL provides the user with the option of

doubling the reference frequency via the enable SYSCLK

doubler bit. Doubling the input reference frequency potentially

reduces the PLL in-band noise. The reference frequency must be

less than 150 MHz when using the 2× frequency multiplier to

satisfy the 300 MHz maximum PFD rate. Furthermore, the 2×

frequency multiplier requires the reference input signal to have

very near to 50% duty cycle; otherwise, the resulting spurious

content may prevent the system clock PLL from locking.

PRESCALE DIVIDER

The system clock PLL includes an input prescale divider

programmable for divide ratios of 1 (default), 2, 4, or 8. The

purpose of the divider is to provide flexible frequency planning

for mitigating potential spurs in the output clock signals of the

AD9542. The user selects the divide ratio via the 2-bit SYSCLK

AD9542 датащи(PDF) 29 Page - Analog Devices

AD9542 датащи(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

датащи скачать

ссылки URL