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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9542 датащи(PDF) 39 Page - Analog Devices |
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AD9542 датащи(HTML) 39 Page - Analog Devices |
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39 / 61 page  Data Sheet AD9542 Rev. 0 | Page 39 of 61 Table 29. Mx Receiver/Driver Bit Field Codes for Mx Control Pins Code Boolean Description 00 AND Logical AND the associated Mx control pin with the other Mx control pins assigned to the same control function. 01 NOT AND Invert the logical state of the associated Mx control pin and AND it with the other Mx control pins assigned to the same control function. 10 OR Logical OR the associated Mx control pin with the other Mx control pins assigned to the same control function. 11 NOT OR Invert the logical state of the associated Mx control pin and OR it with the other Mx control pins assigned to the same control function. The Boolean functionality of aggregated Mx control pins follows a hierarchy whereby logical OR operations occur before logical AND operations. The OR and NOT OR operations are collectively grouped into a single result. A logical AND is then performed using that result and the remaining AND and NOT AND operations. Consider a case where M0, M2, M3, and M6 are all assigned to the input/output update control function; that is, Bits[D6:D0] in Register 0x102 through Register 0x108 = 0x01 (see Table 30). In addition, M0 is assigned for AND operation, M2 for NOT OR operation, M3 for NOT AND operation, and M6 for OR operation (that is, the 2-bit codes in Register 0x100 and Register 0x101 according to Table 29). With these settings, the input/output update function behaves according the following Boolean equation: Input/output update = (!M2 || M6) && M0 && !M3 where: ! is logical NOT. Therefore, an input/output update occurs when M0 is Logic 1 and M3 is Logic 0, and either M2 is Logic 0 or M6 is Logic 1. && is logical AND. || is logical OR. When an Mx control pin acts on a control function individually (rather than as part of a group, per the previous example), the Boolean functionality of the codes in Table 29 reduces to two possibilities. Namely, Code 00 and Code 10 specify a Boolean true (the Mx pin logic state applies to the corresponding control function directly), whereas Code 01 and Code 11 specify a Boolean false (the Mx pin logic state applies to the corresponding control function with a logical inversion). Regarding the source and destination proxy columns in Table 30, the &&, || and ! symbols denote the Boolean AND, OR, and NOT operations, respectively. Table 30. Mx Pin Status and Control Codes Bits[D6:D0] (Hex) Control Function Destination Proxy Status Function Source Proxy (or Description) 0x00 No operation (NOOP) Not applicable Logic 0, static Not applicable 0x01 IO_UPDATE Register 0x000F, Bit D0 Logic 1, static Not applicable 0x02 Device power down Register 0x2000, Bit D0 Digital core clock Not applicable 0x03 Clear watchdog timer Register 0x2005, Bit D7 Watchdog timer timeout Not applicable 0x04 Sync all Register 0x2000, Bit D3 SYSCLK calibration in progress Register 0x3001, Bit D2 0x05 Unassigned Not applicable SYSCLK lock detect Register 0x3001, Bit D0 0x06 Unassigned Not applicable SYSCLK stable Register 0x3001, Bit D1 0x07 Unassigned Not applicable Channel 0 and Channel 1 PLLs locked Register 0x3001, Bit D4 && Bit D5 0x08 Unassigned Not applicable PLL0 locked Register 0x3001, Bit D4 0x09 Unassigned Not applicable PLL1 locked Register 0x3001, Bit D5 0x0A Unassigned Not applicable EEPROM save in progress Register 0x3000, Bit D0 0x0B Unassigned Not applicable EEPROM load in progress Register 0x3000, Bit D1 0x0C Unassigned Not applicable EEPROM fault detected Register 0x3000, Bit D2 || Bit D3 0x0D Unassigned Not applicable Temperature sensor limit alarm Register 0x3002, Bit D0 0x0E Unassigned Not applicable Unassigned Not applicable 0x0F Unassigned Not applicable Unassigned Not applicable 0x10 Clear all IRQ events Register 0x2005, Bit D0 Any IRQ event The logical OR of all triggered IRQ events 0x11 Clear common IRQ events Register 0x2005, Bit D1 Common IRQ event The logical OR of all triggered common IRQ events 0x12 Clear PLL0 IRQ events Register 0x2005, Bit D2 PLL0 IRQ event The logical OR of all triggered PLL0 IRQ events 0x13 Clear PLL1 IRQ events Register 0x2005, Bit D3 PLL1 IRQ event The logical OR of all triggered PLL1 IRQ events 0x14 Unassigned Not applicable REFA demodulator clock Not applicable |
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