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AD9542 датащи(PDF) 32 Page - Analog Devices

номер детали AD9542
подробное описание детали  Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator
PDF  61 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9542 датащи(HTML) 32 Page - Analog Devices

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AD9542
Data Sheet
Rev. 0 | Page 32 of 61
APPLICATIONS INFORMATION
OPTICAL NETWORKING LINE CARD
In this application (shown in Figure 41), the AD9542 is used in
a variety of ways.
In a loop timed (WAN) mode, one of the AD9542 DPLLs locks
to the CDR and is used to remove jitter on the receiver path,
sending that clock to the central timing card, as well as the
framer. In some applications, the AD9542 can also perform a
variety of frequency translation tasks, such as multiplying or
dividing by an FEC ratio, and/or removing jitter from a gapped
clock. The other DPLL cleans jitter and provides clocking to the
transmitter path.
Other tasks include frequency translation and jitter cleaning of
the reference clock from the timing card, as well as seamlessly
managing the reference switching from Timing Card A to
Timing Card B.
Given the continually evolving nature of optical line card
protocols and functions, the functions listed in this section are
by no means exhaustive.
FRAMER/FEC
DESERIALIZER
CDR
FRAMER/FEC
SERIALIZER
LDD
LASER DIODE
POST
AMP
TIA
PHOTO DIODE
Tx
Rx
LINE CARD
OPTICAL MODULE
TO SDH/PDH
OPTICAL
NETWORK
AD9542
FROM TIMING CARD B
FROM TIMING CARD A
Figure 41. Optical Line Card Example



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