FUSB303

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6

Table 3. ORIENT PIN VERSUS ORIENT [1:0] REGISTER BITS MAPPING

CC1 (A5)

CC2 (B5)

STATUS.

ORIENT[1] Bit

STATUS.

ORIENT[0] Bit

ADDR/ORIENT pin

Output

FUSB303 CONNECTED AS A SINK

SNK. Open

SNK. Open

0

0

LOW

SNK. Open

SNK. Rp

1

0

HIGH

SNK. Rp

SNK. Open

0

1

LOW

SNK. Rp (Note 2)

SNK. Rp

0

1

LOW

SNK. Rp

SNK. Rp (Note 2)

1

0

HIGH

FUSB303 CONNECTED AS SOURCE

SRC. Open

SRC. Open

0

0

LOW

SRC. Open or SRC. Ra

SRC. Rd

1

0

HIGH

SRC. Rd

SRC. Open or SRC. Ra

0

1

LOW

SRC. Rd (Note 1)

SRC.Rd

0

1

LOW

SRC. Rd

SRC. Rd (Note 1)

1

0

HIGH

1. Orientation decoded on this pin after a Sink Debug Test System (DTS) attached to FUSB303.

2. Orientation decoded on this pin after a Source Debug Test System (DTS) attached to FUSB303.

High Voltage Tolerance on CCx and VBUS pins

The FUSB303 has additional protection for the type C

connector pins where it can tolerate up to 28V on VBUS,

CC1 and CC2 to protect against any misbehaving Type C

device connect to the FUSB303. If VBUS tolerance is

needed higher than 28V, a 900k

W resistor can be used

externally along with a Transient Voltage Suppressor (TVS)

to achieve almost any higher voltage tolerance dictated by

the TVS chosen.

Dead Battery

If power is not applied to FUSB303 and it is attached to

a Source device, then the Source would pull up the CC line

connected through the cable. The FUSB303 in response will

turn on the pull−down that will bring the CC voltage to

a range that the Source can detect an attached device and turn

on VBUS.

GPIO Mode, Debug and Audio Accessories

When VDD is active and on the trailing edge of EN_N, the

FUSB303 will sample PORT/DEBUG_N to determine if the

FUSB303 operates as a Source (HIGH), Sink (LOW) or

DRP (floating). Subsequently the PORT/DEBUG_N will be

set LOW when a Debug Test System is detected.

If

the

FUSB303

is

configured

as

a

Sink

(PORT/DEBUG_N= LOW upon enable), the FUSB303 will

detect a Debug Test System if Rp is detected on both CC1

and CC2. Devices that support orientation detection will

also have ADDR/ORIENT set based on the levels detected

for CC1 and CC2. ID will be set HIGH−Z.

If

the

device

is

configured

as

a

Source

(PORT/DEBUG_N= HIGH upon enable), the FUSB303

will detect a Debug Test System if Rd is detected on both

CC1 and CC2. Devices that support orientation detection

will also have ADDR/ORIENT set based on the levels

detected for CC1 and CC2. ID will be set LOW.

The FUSB303 also supports DRP toggling for detecting

debug test systems. When PORT/DEBUG_N= float upon

enable, the FUSB303 can detect both Source and Sink debug

test systems depending on how it resolves its role as a Source

or Sink. Then it acts either as a Source or Sink as described

above.

The FUSB303 will report Debug Test System detection

as described above except Source, Sink and DRP roles are

configured via the Portrole register. This Portrole register

setting has higher priority over the PORT/DEBUG_N pin

state for Source/Sink/DRP port role.

The FUSB303 will set INT_N/OUT3 = LOW in GPIO

mode when an Audio Accessory is detected. The FUSB303

register as well when Audio Accessory detection is

configured via the Portrole register.

FORCE.SNK and FORCE.SRC Functionality

In some cases, a device may need to force its role to a Sink

or a Source especially if two DRP devices are connected

together and they have connected in the wrong device role.

In that case, the FUSB303 has incorporated a function that

allows it to be forced into either Sink or Source. However,

if it cannot complete this role change, the FUSB303 will

resume its previous role and flag success or failure with

I_FRC_SUCC and I_FRC_FAIL interrupts respectively.

Remedial Actions

In some cases, a device may start to detect a Source or Sink

but get caught in a loop trying to resolve the detected device.