ADV7481WBBCZ datasheet(21/22 Pages) AD

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Data Sheet

ADV7481

AUDIO PROCESSING

The ADV7481 features an audio processor that handles the

audio extracted from the MHL or HDMI stream by the

HDMI/MHL receiver. It contains an audio mute controller that

can detect a variety of conditions that may result in audible

extraneous noise in the audio output. On detection of these

conditions, a 2-channel linear PCM audio signal can be ramped

down to a mute state to prevent audio clicks or pops.

The audio is output on a single flexible serial digital audio

output port supporting I2S-compatible, left justified, and right

justified audio output modes in master mode only. TDM is also

supported, allowing up to eight audio channels with a sample

rate up to 48 kHz to be transmitted over the single serial digital

audio interface.

MIPI CSI-2 TRANSMITTERS

The ADV7481 features two MIPI CSI-2 transmitters: a four-

lane transmitter (Transmitter A) and a single lane transmitter

(Transmitter B).

The four-lane transmitter consists of four differential data lanes

(DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N, and

DA3P), and a differential clock lane (CLKAN and CLKAP). It

supports four data lanes, two data lanes, and one data lane

muxing options, and can be used to transmit video received on

either the HDMI/MHL receiver (processed through the CP),

the 8-bit digital input port, or the AFE (processed through the

SDP).

The main features of the four-lane MIPI transmitter

(Transmitter A) include

•

Support for 8-bit and 10-bit YCbCr 4:2:2 video modes.

•

Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4

(RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes.

•

Support for video formats ranging from 480i to 1080p, and

display resolutions from VGA to UXGA (certain

restrictions apply to the muxing option, video mode, and

video format that can be selected).

•

Data lanes and clock lane remapping to ease PCB layout.

The single lane transmitter consists of a single differential data

lane (DB0N and DB0P) and a differential clock lane (CLKBN

and CLKBP). It transmits video received on the AFE (processed

through the SDP).

The main features of the single lane MIPI transmitter

(Transmitter B) include

•

Support for 8-bit YCbCr 4:2:2 video mode.

•

Support for 480i and 576i video formats.

INTERRUPTS

The ADV7481 features three interrupt request pins. INTRQ1

and INTRQ2 can be programmed to trigger interrupts based on

various selectable events related to the HDMI/MHL receiver

(video and audio related), the SDP, and the CP. INTRQ3 is

dedicated to events related to the MHL CBUS.

Rev. 0 | Page 21 of 22

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