CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

9

POST OFFICE BOX 655303

f − Frequency − GHz

50

60

70

80

90

100

110

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

CMOS Running,

PECL Off (Mode 10)

SUPPLY CURRENT

vs

FREQUENCY

NOTE: Input swing = 500 mV

Figure 6

CMOS and PECL

Running, No Load

CMOS and PECL Running (Mode 3)

CMOS Off, PECL Running

Package Thermal Resistance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

QFN−16 package thermal resistance

with thermal vias in PCB, See Note 1

4-layer JEDEC test board (JESD51−7) with four

thermal vias of 22-mil diameter each,

airflow = 0 ft/min

40.8

°C/W

NOTE 1: It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good

heat sink.

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

= 125°C is not violated)