CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

1

POST OFFICE BOX 655303

One LVPECL Differential Clock Output and

One LVCMOS Single-Ended Output

LVPECL and LVCMOS Outputs

LVPECL Transitions Minimizing Noise

200-MHz LVCMOS

Common-Mode Range Also Provides VBB

Bias Voltage Output for Single-Ended Input

Signals

description

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock

output pair Y0 and Y0 and one single-ended LVCMOS output Y1. It is specifically designed for driving 50-Ω

transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise

impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are

3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The

CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected

to the unused input as a common-mode voltage reference.

Copyright  2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

QFN PACKAGE

(TOP VIEW)

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VBB

Y0

IN

IN

Y0