CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

8

POST OFFICE BOX 655303

jitter characteristics (continued)

f − Frequency − GHz

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

AMPLITUDE PECL PEAK-TO-PEAK

vs

FREQUENCY

Figure 4

Mode = 1 (Divider: Y0 = 1, Y1 = 1 )

Input Swing = 500 mV

Load = See Figure 11

3.6 V

3.3 V

3 V

2.625 V

2.5 V

2.375 V

Figure 5

f − Frequency − MHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

50

100 150 200 250 300 350 400 450 500

AMPLITUDE CMOS PEAK-TO-PEAK

vs

FREQUENCY

Mode = 1 ( divider: Y0 = 1, Y1 = 1 )

Input Swing = 500 mV

3.6 V

3.3 V

3 V

2.625 V

2.5 V

2.375 V

Load = See Figure 10

supply current electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Supply current

Full load

All outputs enabled and terminated with 50 Ω to

f = 800 MHz for LVPECL outputs and 200 MHz for LVCMOS,

100

mA

No load

Outputs enabled, no output load, f = 800 MHz for LVPECL outputs

85

Supply current, 3-state

0.5

mA