PC87383 datasheet(49/77 Pages) NSC

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6.0 Legacy Functional Blocks (Continued)

Revision 1.1

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6.1

PARALLEL PORT

6.1.1

General Description

The Parallel Port supports all IEEE1284 standard communication modes:

Compatibility (known also as Standard or SPP)

Bi-directional (known also as PS/2)

FIFO

EPP (known also as Mode 4)

ECP (with an optional Extended ECP mode)

6.1.2

Parallel Port Register Map

The Parallel Port includes two groups of runtime registers, as follows:

• A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h)

are used only in Extended ECP mode.

• A group of four registers, used only in Extended ECP mode, accessed by a second level offset.

EPP and second level offset registers are available only when the base address is 8-byte aligned.

The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-

isters and which address bits are used for the base address. See Tables 22 and 23 for a listing of all registers, their offset

addresses and the associated modes. All registers are VDD3 powered.

Table 22. Parallel Port Register Map for First Level Offset

Group

Offset Mnemonic

Type

Mode(s)

Common

Set

000h

DATAR

Data

R/W

Standard, PS/2 and EPP

AFIFO

ECP Address FIFO

ECP

001h

DSR

Status

All Modes

002h

DCR

Control

R/W

All Modes

EPP

Only1

1. These registers are not accessible when the base address is four-byte aligned (i.e. A2=1).

003h

ADDR

EPP Address

R/W

EPP

004h

DATA0

EPP Data Port 0

R/W

005h

DATA1

EPP Data Port 1

R/W

006h

DATA2

EPP Data Port 2

R/W

007h

DATA3

EPP Data Port 3

R/W

PP FIFO,

ECP,

Test and

Conﬁguration

Set

400h

CFIFO

PP Data FIFO

PP FIFO

DFIFO

ECP Data FIFO

R/W

ECP

TFIFO

FIFO Test

R/W

FIFO Test

CNFGA

Conﬁguration A

Conﬁguration

401h

CNFGB

Conﬁguration B

402h

ECR

Extended Control

R/W

All Modes

Extended

Set1, 2

2. These registers are extended to the register set as deﬁned by MS standard. They are accessible only

when enabled by the chip Conﬁguration.

403h

EIR

Extended Index

R/W

404h

EDR

Extended Data

R/W

405h

EAR

Extended Auxiliary Status

R/W

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