PC7410 datasheet(5/54 Pages) ATMEL

5 / 54 page

PC7410

2141D–HIREL–02/04

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Completion of instructions in program order while supporting out-of-order

instruction execution, completion serialization and all instruction flow

changes

•

Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands

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Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

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Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical

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Single-cycle arithmetic, shifts, rotates, logical

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Multiply and divide support (multi-cycle)

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Early out multiply

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Three-stage Floating-point Unit and a 32-entry FPR File

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Support for IEEE-754 standard single- and double-precision floating-point

arithmetic

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Three-cycle latency, one-cycle throughput (single or double precision)

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Hardware support for divide

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Hardware support for denormalized numbers

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Time deterministic non-IEEE mode

•

System Unit

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Executes CR logical instructions and miscellaneous system instructions

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Special register transfer instructions

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AltiVec Unit

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Full 128-bit data paths

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Two dispatchable units: vector permute unit and vector ALU unit

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Contains its own 32-entry 128-bit vector register file (VRF) with six renames

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The vector ALU unit is further sub-divided into the vector simple integer unit

(VSIU), the vector complex integer unit (VCIU) and the vector floating-point

unit (VFPU).

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Fully pipelined

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Load/Store Unit

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One-cycle load or store cache access (byte, half-word, word, double-word)

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Two-cycle load latency with one-cycle throughput

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Effective address generation

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Hits under misses (multiple outstanding misses)

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Single-cycle unaligned access within double-word boundary

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Alignment, zero padding, sign extend for integer register file

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Floating-point internal format conversion (alignment, normalization)

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Sequencing for load/store multiples and string operations

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Store gathering

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Executes the cache and TLB instructions

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Big- and little-endian byte addressing supported

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Misaligned little-endian supported

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Supports FXU, FPU, and AltiVec load/store traffic

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Complete support for all four architecture AltiVec DST streams

•

Level 1 (L1) Cache Structure

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32K 32-byte line, 8-way set associative instruction cache (iL1)

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