PC7410 datasheet(34/54 Pages) ATMEL

34 / 54 page

PC7410

2141D–HIREL–02/04

Notes:

1. OVDD supplies power to the processor bus, JTAG and all control signals except the L2 cache controls (L2CE, L2WE, and

L2ZZ); L2OV

DD supplies power to the L2 cache interface (L2ADDR[0:18], L2ASPARE, L2DATA[0:63], L2DP[0:7] and

L2SYNC_OUT) and the L2 control signals and V

DD supplies power to the processor core and the PLL and DLL (after filtering

to become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a

given signal as selected by the BVSEL/L2VSEL pin configurations of Table 3 and the voltage supplied. For actual recom-

mended value of VIN or supply voltages, see Table 4.

2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OV

(selects 2.5V), GND (selects 1.8V), or to HRESET (selects 2.5V). The PC7410 Both the 60x processor bus and the L2 bus

only support the 1.8 and 2.5 options (see Table 3). the default selection if BVSEL and/or L2VSEL is left unconnected is 2.5V

4. Connect to HRESET to trigger post power-on-reset (por) internal memory test.

L2WE

N16

Low

Output

L2VSEL

L2ZZ

G17

High

Output

L2VSEL

LSSD_MODE(2)

Low

Input

BVSEL

MCP

B11

Low

Input

BVSEL

OVDD

D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4,

R6, R9, R11, T5, T8, T12

N/A

PLL_CFG[0:3]

A4, A5, A6, A7

High

Input

BVSEL

QACK

Low

Input

BVSEL

QREQ

Low

Output

BVSEL

RSRV

Low

Output

BVSEL

SHD0(8)

Low

I/O

BVSEL

SHD1(5)(8)

Low

I/O

BVSEL

SMI

A12

Low

Input

BVSEL

SRESET

E10

Low

Input

BVSEL

SYSCLK

Input

BVSEL

Low

Input

BVSEL

TBEN

High

Input

BVSEL

TBST

A11

Low

Output

BVSEL

TCK

B10

High

Input

BVSEL

TDI(9)

High

Input

BVSEL

TDO

High

Output

BVSEL

TEA

Low

Input

BVSEL

TMS(9)

High

Input

BVSEL

TRST(9)(14)

A10

Low

Input

BVSEL

Low

I/O

BVSEL

TSIZ[0:2]

A9, B9, C9

High

Output

BVSEL

TT[0:4]

C10, D11, B12, C12, F11

High

I/O

BVSEL

Low

I/O

BVSEL

VDD

G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12

N/A

Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)

Signal Name

Pin Number

Active

I/O

I/F Select(1)

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