PC7410 datasheet(39/54 Pages) ATMEL

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PC7410

2141D–HIREL–02/04

Clock Selection

The PC7410’s PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK

(bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency

of operation. The PLL configuration for the PC7410 is shown in Table 17 for example

frequencies. In this example, shaded cells represent settings that, for a given SYSCLK

frequency, result in core and/or VCO frequencies that do not comply with the minimum

and maximum core frequencies listed in Table 11.

Notes:

1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC7410; see “Clock AC Specifications” on page 20

for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use and third- party emulator tool development only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the PC7410 regardless of the SYSCLK input.

5. PLL-off mode should not be used during chip power-up sequencing.

Table 17. PC7410 Microprocessor PLL Configuration

(1)(2)(3)(4)(5)

PLL_CFG

[0:3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

Bus

33.3 MHz

Bus

50 MHz

Bus

66.6 MHz

Bus

75 MHz

Bus

83.3 MHz

Bus

100 MHz

Bus

133 MHz

0100

0110

2.5x

1000

400 (800)

1110

3.5x

350 (700)

465 (930)

1010

400 (800)

0111

4.5x

375 (750)

450 (900)

1011

375 (750)

416 (833)

500 (1000)

1001

5.5x

366 (733)

412 (825)

458 (916)

1101

400 (800)

450 (900)

500 (1000)

0101

6.5x

433 (866)

488 (967)

0010

350 (700)

466 (933)

0001

7.5x

375 (750)

500

(1000)

1100

400 (800)

0000

450 (900)

0011

PLL off/bypass

PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111

PLL off

PLL off, no core clocking occurs

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