9

ATSAM9753

1774D–DRMSD–11/02

Architectural

Overview

The highly integrated architecture from ATSAM9753 combines a specialized high-per-

formance RISC-based digital signal processor (DSP) and a general-purpose 16-bit

CISC-based control processor (P16). An on-chip memory management unit (MMU)

allows the DSP and the control processor to share an internal 32K x 16 RAM as well as

external ROM and/or RAM memory devices. An intelligent peripheral I/O interface func-

tion handles other I/O interfaces, such as the on-chip MIDI UART and three timers, with

minimum intervention from the control processor. A keyboard/switches/sliders/LEDs

autonomous scanning interface handles the specific musical instrument peripherals,

including accurate keyboard velocity detection and communicates with the control pro-

cessor through a dedicated 128 x 16 dual-port RAM. An LCD display interface allows

direct connection to common LCD displays.

DSP Engine

The DSP engine operates on a frame-timing basis with the frame subdivided into 64

process slots. Each process is itself divided into 16 micro-instructions known as algo-

rithms. Up to 32 DSP algorithms can be stored on-chip in the Alg RAM memory,

allowing the device to be programmed for a number of audio signal generation/process-

ing applications.

The DSP engine is capable of generating 64 simultaneous voices using algorithms such

as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for

each voice. Slots may be linked together (ML RAM) to allow implementation of more

complex synthesis algorithms.

A typical musical instrument application will use a little more than half the capacity of the

DSP engine for synthesis, thus providing state-of-the-art 38-voice synthesis polyphony.

The remaining processing power may be used for typical functions such as reverbera-

tion, chorus, surround effect, equalizer, etc.

Frequently-accessed DSP parameter data are stored into five banks of on-chip RAM

memory. Sample data or delay lines that are accessed relatively infrequently are stored

in external ROM, or in the built-in 32K x 16 RAM. The combination of localized micro-

program memory and localized parameter data allows micro-instructions to execute in

22 ns (45 MIPS). Separate buses from each of the on-chip parameter RAM memory

banks allow highly parallel data movement to increase the effectiveness of each micro-

instruction. With this architecture, a single micro-instruction can accomplish up to six

simultaneous operations (add, multiply, load, store, etc.), providing a potential through-

put of 270 million operations per second (MOPS).

P16 Control Processor

and I/O Functions

The P16 control processor is a general-purpose 16-bit CISC processor core, which runs

from external memory. A debug ROM is included on-chip for easy development of firm-

ware directly on the target system. This ROM also contains the necessary code to

directly program externally connected Flash memory. The P16 includes 256 words of

local RAM data memory for use as registers, scratchpad data and stack.

The P16 control processor writes to the parameter RAM blocks within the DSP core in

order to control the synthesis process. In a typical application, the P16 control processor

parses and interprets incoming commands from the MIDI UART or from the scanning

interface and then controls the DSP by writing into the parameter RAM banks in the

DSP core. Slowly changing synthesis functions, such as LFOs, are implemented in the

P16 control processor by periodically updating the DSP parameter RAM variables.

The P16 control processor interfaces with other peripheral devices, such as the system

control and status registers, the on-chip MIDI UART, the on-chip timers and the scan-

ning interface through specialized “intelligent” peripheral I/O logic. This I/O logic