PC7447 datasheet(55/66 Pages) ATMEL

55 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

Connection

Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an

appropriate signal level. Unused active low inputs should be tied to OV

DD. Unused

active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnected. Power and ground connections must be made to all external V

DD,

DD, GVDD, and GND pins in the PC7457. If the L3 interface is not used, GVDD should

be connected to the OV

DD power plane, and L3VSEL should be connected to BVSEL;

the remainder of the L3 interface may be left unterminated.

Output Buffer DC

Impedance

The PC7457 processor bus and L3 I/O drivers are characterized over process, voltage,

and temperature.

To measure Z0, an external resistor is connected from the chip pad to OV

DD or GND.

Then, the value of each resistor is varied until the pad voltage is OV

DD/2 (see Figure 30

on page 50).

The output impedance is the average of two components, the resistances of the pull-up

and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is

trimmed until the voltage at the pad equals OV

DD/2. RN then becomes the resistance of

the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is

trimmed until the voltage at the pad equals OV

DD/2. RP then becomes the resistance of

the pull-up devices. RP and RN are designed to be close to each other in value. Then,

Z0 = (RP + RN)/2.

Figure 32. Driver Impedance Measurement

Table 20 summarizes the signal impedance results. The impedance increases with junc-

tion temperature and is relatively unaffected by bus voltage.

Table 20. Impedance Characteristics with V

DD = 1.5V, OVDD = 1.8V ±5%, Tj = 5° - 85°C

Impedance

Processor bus

L3 Bus

Unit

Typical

33 – 42

34 – 42

Ω

Maximum

31 – 51

32 – 44

Ω

OVDD

OGND

SW2

SW1

Pad

Data

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