PC7447 datasheet(23/66 Pages) ATMEL

23 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and

(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to

the SYSCLK reference (K) going to the high (H) state or input setup time. And t

KHOV symbolizes the time from SYSCLK (K)

going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal

(I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and

output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).

3. tSYSCLK is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of

SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high

before returning to high impedance as shown in Figure 10 on page 24. The nominal precharge width for TS is 0.5 × tSYSCLK,

that is, less than the minimum t

SYSCLK period, to ensure that another master asserting TS on the following clock will not con-

tend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for

precharge.The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.

6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following

AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low

in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second

cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high imped-

ance as shown in Figure 10 on page 24 before the first opportunity for another master to assert ARTRY. Output valid and

output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Tim-

ing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire

cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is

1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).

8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters

represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These

inputs must remain stable after the second sample. See Figure 9 on page 23 for sample timing.

Figure 9. Mode Input Timing Diagram

tMVRH

tMXRH

HRESET

Mode Signals

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