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MP2625BGL датащи(PDF) 26 Page - Monolithic Power Systems |
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MP2625BGL датащи(HTML) 26 Page - Monolithic Power Systems |
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26 / 31 page ![]() MP2625B – SINGLE CELL SWITCHING CHARGER WITH POWER PATH CONTROL MP2625B Rev. 1.01 www.MonolithicPower.com 26 1/15/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. Selecting the Input Capacitor The input capacitor C1 from the typical application circuit absorbs the maximum ripple current from the PWM converter, which is given by MAX _ IN TC MAX _ IN TC MAX _ CC MAX _ RMS V ) V V ( V I I (A) (11) For ICC_MAX=2A, VTC=3V, VIN_MAX=10V, the maximum ripple current is 1A. Select the input capacitors so that the temperature rise due to the ripple current does not exceed 10°C. Use ceramic capacitors with X5R or X7R dielectrics because of their low ESR and small temperature coefficients. For most applications, use a 10µF capacitor. Besides, usually a small cap with at least 1uF (C1) from IN to GND is required to be put as much close as possible to the IC. For the input voltage is high to 10V, consider the spike when input insert, select the input capacitors (both the 22uF and 1uF) in 25V rating. Selecting the Output Capacitor The output capacitor CSYS from the typical application circuit is in parallel with the SYS load. CSYS absorbs the high-frequency switching ripple current and smoothes the output voltage. Its impedance must be much less than that of the system load to ensure it properly absorbs the ripple current. Use a ceramic capacitor because it has lower ESR and smaller size that allows us to ignore the ESR of the output capacitor. Thus, the output voltage ripple is given by: SYS SYS IN 2 SYS SYS S V 1 V V r% V8 C f L (12) In order to guarantee the ±0.5% system voltage accuracy, the maximum output voltage ripple must not exceed 0.5% (e.g. 0.1%). The maximum output voltage ripple occurs at the minimum system voltage and the maximum input voltage. The output capacitor can be calculated with Equation (13): SYS _ MIN IN SYS 2 S V 1 V C 8f L r (13) When SYSFB pin is floating, output voltage ripple is the main concern to select the output capacitor (CSYS), refer to Table 5 for detail selection guide about the SYS capacitance selection under typical inputs. Table 5: SYS Capacitance Selection Guide NOTE: 7) For different voltage rating, capacitance will have different DC bias characteristic. Suppose a general condition, capacitance drops 40% under VSYS=4.4V under 10V rating, and 50% at 6.3V rating. SPEC SYS Capacitance (CSYS) Selection VIN SYS IN SYS 2 S V 1 V C 8f L r ∆r=0.1% L=1uH @VIN=5V L=2.2uH @VIN=9V CSYS_MIN (uF) 7) When SYSFB is Floating CSYS_MIN (uF) 7) When SYSFB is Programmed Temperature Characteristic Package 5V 13.6 20 X5R;X7R Application Required 9V 13.3 20 X5R;X7R Application Required |
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