OXCB950 datasheet(49/68 Pages) ETC

49 / 68 page

Data Sheet Revision 1.1

Page 49

OXCB950

OXFORD SEMICONDUCTOR LTD.

NMR[0]: 9-bit mode enable

logic 0

⇒ 9-bit mode is disabled.

logic 1

⇒ 9-bit mode is enabled.

NMR[1]: Enable interrupt when 9th bit is set

logic 0

⇒ Receiver interrupt for detection of an ‘address’

character (i.e. 9th bit set) is disabled.

logic 1

⇒ Receiver interrupt for detection of an ‘address’

character (i.e. 9th bit set) is enabled and a level

1 interrupt is asserted.

Special Character Detection

While the UART is in both 9-bit mode and Enhanced mode,

setting IER[5] will enable detection of up to four ‘address’

characters. The least significant eight bits of these four

programmable characters are stored in special characters

1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)

registers and the 9th bit of these characters are

programmed in NMR[5] to NMR[2] respectively.

NMR[2]: Bit 9 of Special Character 1

NMR[3]: Bit 9 of Special Character 2

NMR[4]: Bit 9 of Special Character 3

NMR[5]: Bit 9 of Special Character 4

NMR[7:6]: Reserved

Bits 6 and 7 of NMR are always cleared and reserved for

future use.

7.11.10 Modem Disable Mask ‘MDM’

The MDM register is located at offset 0x0E of the ICR

This register is cleared after a hardware reset to maintain

compatibility with 16C550. It allows the user to mask

interrupts, sleep operation and power management events

due to individual modem lines or the serial input line.

MDM[0]: Disable delta CTS

logic 0

⇒ Delta CTS is enabled. It can generate a level 4

interrupt when enabled by IER[3]. In power-

state D2, delta CTS can assert the PME# line.

Delta CTS can wake up the UART when it is

asleep under auto-sleep operation.

logic 1

⇒ Delta CTS is disabled. In can not generate an

interrupt, assert a PME# or wake up the UART.

MDM[1]: Disable delta DSR

logic 0

⇒ Delta DSR is enabled. It can generate a level 4

interrupt when enabled by IER[3]. In power-

state D2, delta DSR can assert the PME# line.

Delta DSR can wake up the UART when it is

asleep under auto-sleep operation.

logic 1

⇒ Delta DSR is disabled. In can not generate an

interrupt, assert a PME# or wake up the UART.

MDM[2]: Disable Trailing edge RI

logic 0

⇒ Trailing edge RI is enabled. It can generate a

level 4 interrupt when enabled by IER[3]. In

power-state D2, trailing edge RI can assert the

PME# line. Trailing edge RI can wake up the

UART when it is asleep under auto-sleep

operation.

logic 1

⇒ Trailing edge RI is disabled. In can not

generate an interrupt, assert a PME# or wake

up the UART.

MDM[3]: Disable delta DCD

logic 0

⇒ Delta DCD is enabled. It can generate a level 4

interrupt when enabled by IER[3]. In power-

state D2, delta DCD can assert the PME# line.

Delta DCD can wake up the UART when it is

asleep under auto-sleep operation.

logic 1

⇒ Delta DCD is disabled. In can not generate an

interrupt, assert a PME# or wake up the UART.

MDM[4]: Reserved

This bit must be set to ‘0’

MDM[5]: Disable SIN wake up

logic 0

⇒ When the device is in power-down state D2, a

change in the state of the serial input line (i.e.

start bit) can assert the PME# line

logic 1

⇒ When the device is in power-down state D2, a

change in the state of the serial input line

cannot assert the PME# line.

MDM[7:6]: Reserved

7.11.11 Readable FCR ‘RFC’

The RFC register is located at offset 0x0F of the ICR

This read-only register returns the current state of the FCR

included for diagnostic purposes.

7.11.12 Good-data status register ‘GDS’

The GDS register is located at offset 0x10 of the ICR

For the definition of Good-data status refer to section

Error! Reference source not found..

GDS[0]: Good Data Status

GDS[7:1]: Reserved

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