Data Sheet Revision 1.1

Page 2

OXCB950

OXFORD SEMICONDUCTOR LTD.

1

PERFORMANCE COMPARISON..................................................................................................4

1.1

IMPROVEMENTS OF THE OXCB950 OVER DISCRETE SOLUTIONS:........................................................................... 4

2

BLOCK DIAGRAM.......................................................................................................................5

3

PIN INFORMATION .....................................................................................................................6

4

PIN DESCRIPTIONS....................................................................................................................7

5

CONFIGURATION & OPERATION .............................................................................................11

6

PCI TARGET CONTROLLER .....................................................................................................12

6.1

OPERATION........................................................................................................................................................................ 12

6.2

CONFIGURATION SPACE ................................................................................................................................................. 13

6.2.1

CARDBUS / PCI CONFIGURATION SPACE REGISTER MAP..................................................................................... 13

6.3

ACCESSING THE UART FUNCTION ................................................................................................................................ 15

6.3.1

CARDBUS/PCI ACCESS TO THE INTERNAL UART.................................................................................................... 15

6.4

ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 16

6.4.1

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ......................................................... 16

6.4.2

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................. 17

6.4.3

UART MIRROR REGISTER ‘UMR’ (OFFSET 0X08): .................................................................................................... 18

6.4.4

GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X0C) ................................................ 19

6.5

CARDBUS/ PCI INTERRUPT ............................................................................................................................................. 20

6.6

CARDBUS/PCI POWER MANAGEMENT.......................................................................................................................... 21

6.6.1

POWER MANAGEMENT VIA UART/ MIO PINS............................................................................................................ 21

6.6.2

POWER REPORTING..................................................................................................................................................... 22

6.6.3

CARDBUS POWER MANAGEMENT ............................................................................................................................. 23

6.7

CARDBUS STATUS REGISTERS ..................................................................................................................................... 24

6.8

CARDBUS TUPLE INFORMATION ................................................................................................................................... 26

7

INTERNAL OX16C950 UART .....................................................................................................27

7.1

OPERATION – MODE SELECTION ................................................................................................................................... 27

7.1.1

450 MODE ....................................................................................................................................................................... 27

7.1.2

550 MODE ....................................................................................................................................................................... 27

7.1.3

750 MODE ....................................................................................................................................................................... 27

7.1.4

650 MODE ....................................................................................................................................................................... 27

7.1.5

950 MODE ....................................................................................................................................................................... 28

7.2

REGISTER DESCRIPTION TABLES ................................................................................................................................. 29

7.3

RESET CONFIGURATION ................................................................................................................................................. 33

7.3.1

HARDWARE RESET....................................................................................................................................................... 33

7.3.2

SOFTWARE RESET ....................................................................................................................................................... 33

7.4

TRANSMITTER AND RECEIVER FIFOS........................................................................................................................... 34

7.4.1

FIFO CONTROL REGISTER ‘FCR’................................................................................................................................ 34

7.5

LINE CONTROL & STATUS............................................................................................................................................... 35

7.5.1

FALSE START BIT DETECTION .................................................................................................................................... 35

7.5.2

LINE CONTROL REGISTER ‘LCR’................................................................................................................................ 35

7.5.3

LINE STATUS REGISTER ‘LSR’.................................................................................................................................... 36

7.6

INTERRUPTS & SLEEP MODE ......................................................................................................................................... 37

7.6.1

INTERRUPT ENABLE REGISTER ‘IER’ ........................................................................................................................ 37

7.6.2

INTERRUPT STATUS REGISTER ‘ISR’ ........................................................................................................................ 38

7.6.3

INTERRUPT DESCRIPTION .......................................................................................................................................... 38

7.6.4

SLEEP MODE ................................................................................................................................................................. 39

7.7

MODEM INTERFACE ......................................................................................................................................................... 39

7.7.1

MODEM CONTROL REGISTER ‘MCR’.......................................................................................................................... 39