LTC2668 datasheet(35/40 Pages) LINER

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LTC2348-16

234816fa

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take effect immediately with no additional analog input

settling time required before starting the next conversion.

It is still possible to read conversion data after starting the

nextconversion,butthiswilldegradeconversionaccuracy

and therefore is not recommended.

Just prior to the falling edge of BUSY and the opening

of a new data transaction window, SDO is updated with

the latest conversion results from analog input channel

0. Both rising and falling edges on SCKI serially clock

conversionresultsandanaloginputchannelconfiguration

information out on SDO. SCKI is also echoed on SCKO,

skew-matched to the data on SDO. Whenever possible, it

is recommended that rising and falling edges of SCKO be

used to capture DDR serial output data on SDO, as this will

yield the best robustness to delay variations over supply

and temperature. SCKI rising and falling edges also latch

SoftSpan configuration words provided on SDI, which are

used to program the internal 24-bit SoftSpan configura-

tion register. See the section Programming the SoftSpan

Configuration Register in LVDS I/O Mode for further

details. As shown in Figure 21, the LVDS bus is enabled

when CS is low and is disabled and Hi-Z when CS is high,

allowing the bus to be shared across multiple devices.

Due to the high speeds involved in LVDS signaling, LVDS

bus sharing must be carefully considered. Transmission

line limitations imposed by the shared bus may limit the

maximum achievable bus clock speed. LVDS inputs are

internallyterminatedwitha100Ωdifferentialresistorwhen

CS is low, while outputs must be differentially terminated

with a 100Ω resistor at the receiver (FPGA). SCKI must

idle in the low state in LVDS I/O mode, including when

transitioning CS.

The data on SDO are grouped into 24-bit packets consist-

ing of a 16-bit conversion result plus 2-bit trailing zero

pad, 3-bit analog channel ID, and 3-bit SoftSpan code, all

presented MSB first. As suggested in Figures 20 and 21,

SDO outputs these packets for all analog input channels

in a sequential, circular manner. For example, the first

24-bit packet output on SDO corresponds to analog input

channel 0, followed by the packets for channels 1 through

7. The data output on SDO then wraps back to channel 0,

and this pattern repeats indefinitely.

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

25 26

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5

D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0

SS1

SS2

SS0 D15 D14 D13

CNV

(CMOS)

CS = PD = 0

234816 F20

DON’T CARE

tACQ

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

SAMPLE N

tCNVL

tCYC

RECOMMENDED DATA TRANSACTION WINDOW

SAMPLE N + 1

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

CHANNEL 0

24-BIT PACKET

CONVERSION N

CHANNEL 1

24-BIT PACKET

CONVERSION N

CHANNEL 7

24-BIT PACKET

CONVERSION N

CONVERSION RESULT

CHANNEL ID SoftSpan

186

185

187 188 189 190 191 192

SS1

SS2

SS0 D15

CHANNEL 0

24-BIT PACKET

CONVERSION N

CONVERSION

RESULT

CHANNEL ID SoftSpan

tSKEW

tCNVH

tSCKIH

tSCKIL

tBUSYLH

tDSDOSCKI

tHSDOSCKI

tDSDOBUSYL

tSSDISCKI

tHSDISCKI

tQUIET

tSCKI

tCONV

C2 C1 C0

Figure 20. Serial LVDS I/O Mode

applicaTions inForMaTion

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