LTC2668 datasheet(29/40 Pages) LINER

29 / 40 page

LTC2348-16

234816fa

For more information www.linear.com/LTC2348-16

POWER CONSIDERATIONS

The LTC2348-16 requires four power supplies: the posi-

tive and negative high voltage power supplies (VCC and

VEE), the 5V core power supply (VDD) and the digital input/

output (I/O) interface power supply (OVDD). As long as

the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V

are observed, VCC and VEE may be independently biased

anywhere within their own individual allowed operating

ranges, including the ability for either of the supplies to be

tied directly to ground. This feature enables the common

mode input range of the LTC2348-16 to be tailored to the

specificapplication’srequirements.TheflexibleOVDDsup-

ply allows the LTC2348-16 to communicate with CMOS

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems. When using LVDS I/O mode, the range of

OVDD is 2.375V to 5.25V.

Power Supply Sequencing

The LTC2348-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2348-16 has

an internal power-on-reset (POR) circuit which resets the

converter on initial power-up and whenever VDD drops

below 2V. Once the supply voltage re-enters the nominal

supply voltage range, the POR reinitializes the ADC. No

conversions should be initiated until at least 10ms after

a POR event to ensure the initialization period has ended.

Whenemployingtheinternalreferencebuffer,allow200ms

forthebuffertopowerupandrechargetheREFBUFbypass

capacitor. Any conversion initiated before these times will

produce invalid results.

TIMING AND CONTROL

CNV Timing

TheLTC2348-16samplingandconversioniscontrolledby

CNV. A rising edge on CNV transitions all channels’ S/H

circuits from track mode to hold mode, simultaneously

sampling the input signals on all channels and initiating

a conversion. Once a conversion has been started, it

cannot be terminated early except by resetting the ADC,

as discussed in the Reset Timing section. For optimum

performance, drive CNV with a clean, low jitter signal and

avoid transitions on data I/O lines leading up to the rising

edgeofCNV.Additionally,tominimizechannel-to-channel

crosstalk, avoid high slew rates on the analog inputs for

100ns before and after the rising edge of CNV. Converter

status is indicated by the BUSY output, which transitions

low-to-high at the start of each conversion and stays high

untiltheconversioniscomplete. OnceCNVisbroughthigh

to begin a conversion, it should be returned low between

40ns and 60ns later or after the falling edge of BUSY to

minimizeexternaldisturbancesduringtheinternalconver-

sion process. The CNV timing required to take advantage

of the reduced power nap mode of operation is described

in the Nap Mode section.

Internal Conversion Clock

The LTC2348-16 has an internal clock that is trimmed to

achieve a maximum conversion time of 550•N ns with N

channels enabled. With a minimum acquisition time of

570ns when converting eight channels simultaneously,

throughputperformanceof200kspsisguaranteedwithout

any external adjustments.

applicaTions inForMaTion

CNV

tCONV

tACQ

BUSY

NAP

NAP MODE

tCNVL

234816 F14

Figure 14. Nap Mode Timing for the LTC2348-16

LTC2668 датащи(PDF) 29 Page - Linear Technology

LTC2668 датащи(HTML) 29 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL