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LTC2348-16

234816fa

For more information www.linear.com/LTC2348-16

Nap Mode

The LTC2348-16 can be placed into nap mode after a con-

versionhasbeencompletedtoreducepowerconsumption

between conversions. In this mode a portion of the device

circuitry is turned off, including circuits associated with

sampling the analog input signals. Nap mode is enabled

by keeping CNV high between conversions, as shown in

Figure 14. To initiate a new conversion after entering nap

mode, bring CNV low and hold for at least 420ns before

bringingithighagain.Theconverteracquisitiontime(tACQ)

is set by the CNV low time (tCNVL) when using nap mode.

Power Down Mode

When PD is brought high, the LTC2348-16 is powered

down and subsequent conversion requests are ignored. If

this occurs during a conversion, the device powers down

once the conversion completes. In this mode, the device

draws only a small regulator standby current resulting in a

typical power dissipation of 0.36mW. To exit power down

mode, bring the PD pin low and wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

Reset Timing

A global reset of the LTC2348-16, equivalent to a power-

on-reset event, may be executed without needing to cycle

the supplies. This feature is useful when recovering from

system-level events that require the state of the entire sys-

tem to be reset to a known synchronized value. To initiate

a global reset, bring PD high twice without an intervening

conversion, as shown in Figure 15. The reset event is trig-

geredonthesecondrisingedgeofPD,andasynchronously

applicaTions inForMaTion

ends based on an internal timer. Reset clears all serial data

outputregistersandrestorestheinternalSoftSpanconfigu-

ration register default state of all channels in SoftSpan 7.

If reset is triggered during a conversion, the conversion

is immediately halted. The normal power down behavior

associatedwithPDgoinghighisnotaffectedbyreset.Once

PD is brought low, wait at least 10ms before initiating a

conversion. When employing the internal reference buffer,

allow 200ms for the buffer to power up and recharge the

REFBUF bypass capacitor. Any conversion initiated before

these times will produce invalid results.

Power Dissipation vs Sampling Frequency

When nap mode is employed, the power dissipation of

the LTC2348-16 decreases as the sampling frequency is

reduced, as shown in Figure 16. This decrease in aver-

age power dissipation occurs because a portion of the

LTC2348-16 circuitry is turned off during nap mode, and

the fraction of the conversion cycle (tCYC) spent napping

increases as the sampling frequency (fSMPL)isdecreased.

IOVDD

IVDD

IVEE

IVCC

WITH NAP MODE

tCNVL = 1µs

SAMPLING FREQUENCY (kHz)

120

160

200

–4

–2

234816 F16

Figure 16. Power Dissipation of the LTC2348-16

Decreases with Decreasing Sampling Frequency

CNV

tCONV

tCNVH

tPDH

tPDL

BUSY

RESET

RESET TIME

SET INTERNALLY

SECOND RISING EDGE OF

PD TRIGGERS RESET

tWAKE

234816 F15

Figure 15. Reset Timing for the LTC2348-16

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