LTC2876 datasheet(17/32 Pages) LINER

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LTC2876/LTC2877

28767fa

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Balanced Signal Threshold

The LTC2876/LTC2877 differential threshold is 120mV

for rising input signals and –120mV for falling signals.

This constitutes 240mV of hysteresis, which offers a high

rejection to signal noise that can otherwise falsely trip

a receiver. Since these thresholds are centered around

zero volts (i.e. “balanced”), the duty cycle is preserved

for small amplitude signals with slewed edges—typical

of what is observed at the end of a long cable. Figure 11

illustrates this point.

In contrast to this, some RS485 receivers have an un-

balanced receiver threshold, used to address failsafe

conditions (more on this below). That is, the rising and

falling differential signal thresholds are both negative.

Figure 12 illustrates an example where the rising threshold

is –75mV and falling threshold is –120mV. This has two

disadvantages. First, the hysteresis is only 45mV in this

example, reducing the tolerance to noise, compared to the

240mV of hysteresis in the LTC2876/LTC2877. Secondly,

these unbalanced thresholds cause a duty cycle or pulse

width distortion at the receiver output relative to the input

signal. Figure 12 illustrates how a competitor part, using

the negative thresholds in this example introduces a duty

cycle distortion that becomes increasingly worse with low

input signal levels and slow input edge rates.

Failsafe Operation

The LTC2876 and LTC2877 have a failsafe feature that

guarantees the receiver output will be in a logic 1 state

(the idle state) when the inputs are shorted, left open, or

terminated but not driven for more than about 1.5µs. This

failsafe feature is guaranteed to work for inputs spanning

the entire common mode range of –25V to +25V.

ManyRS485receiverssimplyemployanegativethreshold

(forrisingandfallingsignals)toachievefailsafeoperation.

If the inputs are shorted together (0V differential), the

receiver produces a high output, consistent with failsafe.

However, this asymmetrical threshold comes with the

disadvantages of pulse width distortion and sensitivity to

signal noise as described in the section above.

The LTC2876/LTC2877 achieves full failsafe operation,

whilereapingthebenefitsofabalancedreceiverthreshold.

Figure 11. The LTC2876/LTC2877 Balanced Signal Threshold

Voltages Preserve the Duty Cycle of an Incoming Signal. The

Differential Signal Received (Top) Has a Duty Cycle of 50%,

and Is Reflected In the Receiver Output, RO (Bottom)

Figure 12. Typical Competitor Unbalanced Signal Threshold

Voltages Distort the Duty Cycle of an Incoming Signal. Input Is

50% Duty Cycle (Top) But the Receiver Output Is Not 50% Duty

Cycle (Bottom)

+200mV

–200mV

VTS+

VTS–

–120mV

+120mV

(PB–PA)

LTC2876, LTC2877 - BALANCED THRESHOLDS

28767 F11

+200mV

–200mV

VTS+

VTS–

–120mV

–75mV

(PB–PA)

UNBALANCED THRESHOLDS

28767 F12

Failsafe operation is performed with a window compara-

tor to determine when the differential input voltage falls

between the rising and falling signal thresholds (VTS+,

and VTS–). If this condition persists for more than about

1.5µs then the receiver switches over to using the failsafe

thresholds (VTFS–, VTFS+), as illustrated in Figure 13 and

Figure14.Thedelayallowsnormaldatasignalstotransition

through the threshold region without being interpreted as

a failsafe condition, and thus maintaining the benefits of a

balancedthresholdreceiver. However,forfaultconditions

(e.g., shorted, open, or undriven lines) that persist for

more than 1.5µs, the failsafe thresholds are engaged and

the receiver output drives high, indicating this condition.

The failsafe delay also prevents unwanted receiver output

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