9

LTC2601/LTC2611/LTC2621

2601f

SDO (Pin 1): Serial Interface Data Output. The serial

output of the shift register appears at the SDO pin. The data

transferred to the device via the SDI pin is delayed 32 SCK

rising edges before being output at the next falling edge.

This pin is used for daisy-chain operation.

SDI (Pin 2): Serial Interface Data Input. Data is applied to

SDI for transfer to the device at the rising edge of SCK

(Pin 3). The LTC2601 accepts input word lengths of either

24 or 32 bits.

SCK (Pin 3): Serial Interface Clock Input. CMOS and TTL

compatible.

CLR (Pin 4): Asynchronous Clear Input. A logic low at this

level-triggered input clears all registers and causes the

DAC voltage outputs to drop to 0V. CMOS and TTL

compatible.

CS/LD (Pin 5): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on SDI

into the register. When CS/LD is taken high, SCK is

disabled and the specified command (see Table 1) is

executed.

REF (Pin 6): Reference Voltage Input. 0V

GND (Pin 8): Analog Ground.

LDAC (Pin 10): Asynchronous DAC Update Pin. If CS/LD

is high, a falling edge on LDAC immediately updates the

DAC register with the contents of the input register (simi-

lar to a software update). If CS/LD is low when LDAC goes

low, the DAC register is updated after CS/LD returns high.

A low on the LDAC pin powers up the DAC. A software

power down command is ignored if LDAC is low.

Exposed Pad (Pin 11): Ground. Must be soldered to PCB

ground.