LTM2893 datasheet(22/32 Pages) LINER

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LTM2893/LTM2893-1

28931fb

For more information www.linear.com/LTM2893

TIMING DIAGRAMS

Figure 9. Logic Side Interface of ADC

frequency = 100MHz) to mask the propagation delay of the

CNV signal to the isolated ADC and the return of the first

two bits in the SPI result. Once the LTM2893 has received

the first two bits from the ADC and stored them in the logic

side serial buffer, the BUSY signal goes low indicating the

data is ready for reading. The SS input is driven low by the

host controller to enable the SPI serial interface. The MSB

of the ADC result is set on the MISOA and MISOB pins.

MISOA output results correspond to the data read into the

MISOA2 isolated input, MISOB output result corresponds

to the data read into the MISOB2 isolated input. MISOA

and MISOB will contain two independent serial output

streams of the specified WORDLENGTH. After the MSB of

the MISOA and MISOB data is available the host controller

can clock the SCK signal the specified number of times

to read in the full ADC result or pair of results. The host

must release the SS signal shortly after the final SCK. The

fault monitor counts the time between SS transitions and

SCK rising edges for stall conditions. Connect a resistor

from MISOB to GND and connect MISOB2 to GND2 if the

second SPI data path is not used.

The LTM2893 uses the SS signal as a framing signal

around the data transfer of the SPI data. However, the

SS signal can be held low continuously if only one or

one pair of simultaneously sampled ADCs exists on the

isolated side and the logic side SPI bus is not shared by

other peripherals. In the event that a fault occurs the SS

signal must be driven high to allow the FAULT flag to be

cleared on the next transaction.

ISOLATED INTERFACE LTM2893

The LTM2893 autonomously interacts with the isolated

ADC when a CNV is initiated. The isolated side CNV2 is

asserted to the ADC and the LTM2893 watches for a rising

edge on BUSY2 and BUSYS. After the BUSY2 or BUSYS

goes high and then low, the isolated side of the LTM2893

will begin reading the ADC. During the SPI read, both

MISOA2 and MISOB2 are captured in parallel using the

same SCK and SS signal. If a single ADC is used with one

MISOA2 connection, connect MISOB2 to GND2. Once the

SPI transaction is complete the LTM2893 is ready for an

additional conversion request on CNV.

CNV

BUSY

ADC CONVERSION TIMING DIAGRAM WITH SS AS CHIP SELECT LOGIC SIDE INTERFACE

SCK

MISOA

D17

tDCNV + tCNV2toADCstart + tCNVADC + tBUSY2FBUSYF

tBUSYLH

ADC CYCLE TIME

ADC ACQUISITION TIME

tQUIET

tDATAREAD

tSCKSSDIS

MISOB

MOSI

LTM2893-1

tBUSYFSCKR

tHDMOSI

2893 F09

tSUMOSI

tCNVH

tSSFSCK

tDMISOSSF

tDMISO

tHMISO

tSCKL

tSCKH

tSCK

tDIS

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