LTM2893 datasheet(13/32 Pages) LINER

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LTM2893/LTM2893-1

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APPLICATIONS INFORMATION

DIGITAL INTERFACE

The LTM2893 has a serial digital interface. The flexible VL

supply allows the LTM2893 to communicate with digital

logic operating between 1.71V and 5.5V, including 2.5V

and 3.3V systems. The serial digital interface matches the

characteristics of a serial peripheral interface bus (SPI)

mode (0, 0) with a minor variation that data is captured

on the rising edge and changes after the rising edge for

SCK2 frequencies of 100MHz and 66MHz, except for

MOSI2 on the LTM2893-1, which changes data on the

falling edge of SCK2 in all cases. This variation allows for

additional propagation and setup time to the next rising

clock (SCK) edge, and should be transparent in most ap-

plications. For SCK2 frequencies of 50MHz or less, data

is captured on the rising edge of SCK and changes on the

falling edge of SCK.

The serial output data is clocked out on the MISO pin when

SS is low and an external clock is applied to the SCK pin.

Clocking out the data immediately after the BUSY signal

goes low will yield the best performance. When SS is high,

the MISOA and MISOB pins are high impedance.

The serial digital interface is monitored by the fault detec-

tion system watchdog for conditions that are considered

a stalled process. Input timing is monitored for delays

longerthantWATCHDOG_TIMEOUTbetweentherisingedgesof

adjacent SCKs. The SCKs are counted and if the expected

number is exceeded, the FAULT output will go low.

The rise and fall time of the logic signals into and out

of the serial digital interface are approximately 1ns or

less. Careful routing between the master device and the

LTM2893 are necessary to avoid reflections resulting in

incorrect data sampling or double clocking. Short direct

routing with ground shielding is necessary. Avoid adding

stubs to the signal routing as these may cause reflections.

STARTUP

The LTM2893 has an internal startup communication rou-

tine to verify both sides of the isolation barrier are ready

for communication. The startup routine is initiated when

voltage is supplied to VCC and VCC2 inputs above 2.75V, VL

and VL2inputsabove1.5V,thelogicsideONsignalishigh,

and the Isolated ON2 signal is high. The BUSY signal will

go high and then low indicating the two internal isolators

have completed the communication startup routine. Once

the BUSY output goes low, the system is ready.

The isolated ON2 pin can be controlled by an external volt-

age supervisor to delay the system ready signal until all

isolatedsuppliesandsystemsareready.Anexampleofthis

is demonstrated in Figure 16 with a LTC2917 configurable

voltage supervisor. The logic side BUSY signal will stay

high until the isolated side supervisor has verified the

supplies are above the specified voltage.

BUSY INDICATOR (LOGIC SIDE)

The BUSY output pin goes high under three conditions:

at startup, during data conversion, and when a watchdog

timeout occurs. During normal operation, after a CNV

rising edge, a high on the BUSY output indicates the ADC

is currently converting an ADC result and is de-asserted

when the data is ready to be read from MISOA and MISOB.

Wait for the BUSY output to go low and wait a tSSFSCK

delay before initiating the first SCK after SS is set low. This

delay allows the most significant bit to be setup properly.

During startup the BUSY output is set high to indicate the

LTM2893 is powering up and will be de-asserted when

isolated communication is verified.

If a watchdog time-out occurs the BUSY signal will go

high and the FAULT pin will go low.

BUSY2 AND BUSYS INPUTS (ISOLATED SIDE)

The isolated side signals BUSY2 and BUSYS control when

the LTM2893 reads data from the ADC(s). Multiple con-

figurationsofthetwoisolatedbusysignalsexist.Internally,

the BUSY2 and the BUSYS input are logically OR-ed into

a single busy response for which the falling edge is used

to trigger the ready to read isolated SPI port function.

If a single ADC is connected to the LTM2893, the ADC

BUSY output connects to the BUSY2 signal and BUSYS

is connected to GND2, see Figure 14. Once the BUSY2

signal goes high then low, a SPI transaction will begin.

ADCs that contain a sleep function when two conversion

start events are triggered without a SPI read must be

treated differently. The LTM2893 does not wake up ADCs

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