MP5021 – 12V, 7

MP5021 Rev. 1.1

www.MonolithicPower.com

14

1/30/2013

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Power-Good

The power-good indicates whether the output

voltage is in the normal range relative to the input

voltage, and is the open drain of a FET. Pull up

the PG pin to the external power supply through

a 100kΩ resistor. During power-up the power-

good output is driven low. This directs the system

to remain off and minimize the OUT load to

reduce in-rush current and power dissipation

during start-up.

When the device reaches the following conditions:

The power-good signal is pulled high. The

system can now draw full power.

When the FB voltage drops below 0.535V, the

low.

The PG output is pulled low when either the EN

pin is below its threshold or the input

UVLO/OVLO is triggered.

With no input, the power good stays at a logic

low level in the presence of a pull-up supply.

FLTB Pin

The fault bar (FLTB) pin is an open drain output

used to indicate that a fault has occurred. Pull up

the FLTB pin to external power supply through a

100kΩ resistor.

When the device reaches its current limit, the die

temperature exceeds the thermal shutdown

threshold, or the MOSFET is shorted before

power-up, the fault output is driven low with a

10µs propagation delay. If a short occurs and the

current reaches its 25A secondary current limit,

The FLTB goes high when the MP5021 resumes

normal operation, which means the output

voltage exceeds the setting voltage of the PG-

rising threshold and power FET is fully ON

External Pull-Up Voltage for PG and FLTB

The PG and FLTB need an external power

supply. The open-drain output of PG can work

well from the external pull-up voltage even when

resistor for PG and FLTB.

Power-Up Sequence

For hot-swappable applications, the input of the

MP5021 can experience a voltage spike or

transient during the hot-plug procedure. This

spike is caused by the parasitic inductance of the

input trace and the input capacitor. An insertion

delay determined by the external capacitor at the

TIMER pin stabilizes the input voltage.

As per Figure 4 (EN floating), the input voltage

rises immediately, and a 30Ω resistor pulls the

TIMER

t

t1

4uA gate charge

1.23V

Insertion Delay Time

UVLO

30O Pull down

40uA

SS

4V clamp

5V

PG

Figure 4: Start-Up Sequence

The TIMER pin charges through a 40µA

constant-current source when the input voltage

reaches the UVLO threshold. When the TIMER

pin voltage reaches 1.23V, a 4µA current source

pulls up the power FET’s gate-source voltage.

Meanwhile, the TIMER pin voltage drops. Once

output voltage rises. The soft-start capacitor

determines the rise time.

Soft-Start

A capacitor connected to the SS pin determines

the soft-start time: When the insertion delay time

ends,

a

constant-current

source

that

is

proportional to the input voltage ramps up the

voltage on the SS pin. The output voltage rises at

a similar slew rate to the SS voltage.