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MP8764GLE датащи(PDF) 18 Page - Monolithic Power Systems |
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MP8764GLE датащи(HTML) 18 Page - Monolithic Power Systems |
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18 / 23 page ![]() MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP MP8764 Rev. 1.2 www.MonolithicPower.com 18 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. APPLICATION INFORMATION Setting the Output Voltage-Large ESR Caps For applications that electrolytic capacitor or POS capacitor with a controlled output of ESR is set as output capacitors. The output voltage is set by feedback resistors R1 and R2. As figure 10 shows. R1 R2 ESR POSCAP SW VOUT L FB Figure 10—Simplified Circuit of POS Capacitor First, choose a value for R2. R2 should be chosen reasonably, a small R2 will lead to considerable quiescent current loss while too large R2 makes the FB noise sensitive. It is recommended to choose a value within 5k - 50k for R2, using a comparatively larger R2 when VOUT is low, and a smaller R2 when VOUT is high. Then R1 is determined as follow with the output ripple considered: OUT OUT REF REF 1 V V V 2 R1 R2 V − × ∆ − = × (15) OUT V ∆ is the output ripple determined by equation 24. Setting the Output Voltage-Small ESR Caps R1 R2 Ceramic SW FB VOUT L R9 R4 C4 Figure 11—Simplified Circuit of Ceramic Capacitor When low ESR ceramic capacitor is used in the output, an external voltage ramp should be added to FB through resistor R4 and capacitor C4.The output voltage is influenced by ramp voltage VRAMP besides resistor divider as shown in figure 11. The VRAMP can be calculated as shown in equation 7. R2 should be chosen reasonably, a small R2 will lead to considerable quiescent current loss while too large R2 makes the FB noise sensitive. It is recommended to choose a value within 5k -50k for R2, using a comparatively larger R2 when VOUT is low, and a smaller R2 when VOUT is high. And the value of R1 then is determined as follow: 9 R 4 R 2 R V V V 2 R 1 R ) AVG ( FB OUT ) AVG ( FB + − − = (16) The VFB(AVG) is the average value on the FB. VFB(AVG) varies with the VIN, VOUT, and load condition, etc.. Its value on the skip mode would be lower than that of the PWM mode, which means the load regulation is strictly related to the VFB(AVG). Also the line regulation is related to the VFB(AVG) ,if one wants to gets a better load or line regulation, a lower VRAMP is suggested once it meets equation 9. For PWM operation, VFB(AVG) value can be deduced from equation 17. RAMP REF AVG FB V V V × + = 2 1 ) ( (17) Usually, R9 is set to 0 , and it can also be set following equation 18 for a better noise immunity. It also should be set to be 5 timers smaller than R1//R2 to minimize its influence on VRAMP. 1 R1 R2 R9 5 R1 R2 × < × + (18) Using equation 16 and 17 to calculate the output voltage can be complicated. To simplify the calculation of R1 in equation 11, a DC-blocking capacitor CDC can be added to filter the DC influence from R4 and R9. Figure 12 shows a simplified circuit with external ramp compensation and a DC-blocking capacitor. With this capacitor, R1 can easily be obtained by using equation 19 for PWM mode operation. |
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