MP8764 ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER WITH LATCH-OFF OCP

MP8764 Rev. 1.2

www.MonolithicPower.com

16

6/21/2016

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If the MP8764 doesn’t work, the PG pin is also

pulled low even though this pin is tied to an

external DC source through a pull-up resistor(e.g.

100k).

Over-Current Protection (OCP)

The MP8764 features three current limit levels for

over-current conditions: high-side peak current

limit, low-side valley current limit and low-side

negative current limit.

High-side peak current limit: MP8764 has cycle-

by-cycle over-current limiting function. During

HS-FET ON state, the inductor current is

monitored. When the sensed inductor current hits

the peak current limit, the HS limit comparator

(shown in Figure 1) turns over, the device enters

over-current protection mode immediately, turns

off HS-FET and turns on LS-FET.

Low-side valley current limit: During LS-FET ON

state, the inductor current is also monitored. At

the end of OFF time, the LS-FET sourcing

current is compared to the internal positive valley

current limit. If the LS-FET sourcing current is

exceeded the valley current limit, the HS-FET is

not turned on and the LS-FET keeps on for the

next ON time. Until the LS-FET sourcing current

is below the valley current limit the HS-FET is

turned on again.

After soft-start ends, if the over-current condition

holds 180us, or VFB<300mV and current limit is

triggered, MP8764 will trigger latch off protection.

Low-side negative current limit: If the LS-FET

sensed negative current exceeds the negative

current limit, e.g. over-voltage protection (OVP)

the LS-FET is turned off immediately for the the

rest of OFF time. In this situation, both MOSFETs

are off until the end of a fixed interval. The body

diode of HS-FET conducts the inductor current

for the fixed time.

Over -voltage Protection (OVP)

The MP8764 monitors the output voltage through

a resistor divider feedback (FB) voltage to detect

over-voltage on the output.

If the FB voltage is higher than nominal REF

voltage but lower than 120% of the REF voltage

(0.611V), both MOSFETs are off,

When the FB voltage is higher than 120% but

lower than 130% of the REF voltage, the LS-FET

will be turned on while the HS-FET keeps off.

The LS-FET keeps on until the FB voltage drops

below 110% of the REF voltage or the low-side

negative current limit is trigged.

If the FB voltage is higher than 130% of the REF

voltage, then the device is latched off. Cycling

the input power supply or EN is needed to restart.

UVLO protection

The

MP8764

has

under-voltage

lock-out

protection (UVLO). When the VCC voltage is

higher than the UVLO rising threshold voltage,

the MP8764 will be powered up. It shuts off when

the VCC voltage is lower than the UVLO falling

threshold voltage. This is non-latch protection.

The MP8764 is disabled when the VCC voltage

falls below 3.3 V. If an application requires a

higher under-voltage lockout (UVLO), use the EN

pin as shown in Figure 9 to adjust the startup

input voltage by using two external resistors. It is

recommended to use the enable resistors to set

to provide enough hysteresis to allow for any

input supply variations.

EN Comparator

IN

EN

Figure 9—Adjustable UVLO