LM9801 datasheet(5/34 Pages) NSC

5 / 34 page

DC and Logic Electrical Characteristics (Continued)

The following specifications apply for AGND e DGND e DGND(IO) e 0V VA e VD ea50VDC VD(IO) ea50 or

30VDC REF IN ea1225VDC fMCLK e 20 MHz Rs e 25X Boldface limits apply for TA e TJ e TMIN to TMAX all

other limits TA e TJ e 25 C (Notes 7 and 8)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 9)

(Note 10)

(Limits)

POWER SUPPLY CHARACTERISTICS

Analog Supply Current

Operating

mA (max)

Standby

Digital Supply Current

Operating

mA (max)

MCLK e 065

ID(IO)

Digital IO Supply Current

Operating VD(IO) e 50V

mA (max)

Operating VD(IO) e 30V

mA (max)

MCLK e 0 VD(IO) e 50V or 30V

AC Electrical Characteristics MCLK Independent

The following specifications apply for AGND e DGND e DGND(IO) e 0V VA e VD e VD(IO) ea50VDC REF IN e

1225VDC fMCLK e 20 MHz tMCLK e 1fMCLK tr e tf e 5 ns Rs e 25X CL (databus loading) e 50 pFpin Boldface

limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 7 and 8)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 9)

(Note 10)

(Limits)

fMCLK

Maximum MCLK Frequency

MHz (min)

Minimum MCLK Frequency

MHz (max)

MCLK Duty Cycle

% (min)

% (max)

SYNC Setup of MCLK

ns (min)

tCDSETUP

Correction Data Valid to CLK Setup

ns (min)

tCDHOLD

Correction Data Valid to CLK Hold

ns (min)

tD1H tD0H

RD High to DD0 – DD7 TRI-STATE

ns (max)

tDACC

Access Time Delay from RD Low to

ns (max)

DD0 – DD7 Data Valid

fSCLK

Maximum SCLK Frequency

MHz (min)

SCLK Duty Cycle

% (min)

% (max)

tSDI

SDI Set-Up Time from SCLK

ns (min)

Rising Edge

tHDI

SDI Hold Time from SCLK

ns (min)

Rising Edge

tDDO

Delay from SCLK Falling Edge to

ns (max)

SDO Data Valid

tHDO

SDO Hold Time from SCLK

RL e 3k CL e 50 pF

ns (max)

Falling Edge

ns (min)

tDELAY

DELAY from SCLK Falling Edge to

ns (min)

CS Rising or Falling Edge

tSETUP

Set-Up Time of CS Rising or Falling

ns (min)

Edge to SCLK Rising Edge

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