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LM9801 датащи(PDF) 28 Page - National Semiconductor (TI) |
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LM9801 датащи(HTML) 28 Page - National Semiconductor (TI) |
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28 / 34 page ![]() Applications Information (Continued) TLH12814 – 40 FIGURE 13 Parallel Output CCD Timing To maximize the integration time for the Red Green and Blue photodiodes the transfer (TR) pulses should be stag- gered as shown in Figure 13 This is done by a demultiplex- er (Mux 2) between the TR output of the LM9801 and the transfer gate inputs of the CCD If the CCD’s transfer gate input capacitance is relatively low (see the CCD datasheet for this specification and the requirements for TR pulse rise and fall time) then the other half of the 74HC4052 may be used to switch the TR pulses as shown If the TR gate input capacitance is so large that the minimum TR rise and fall times can not be met because of the 200X max on resist- ance of the 74HC4052’s switches then the 74HC4052 can not be used to multiplex the TR output and should be re- placed with an active device such as the 74HC155 dual 2- to-4 demultiplexer Two signals (A and B) must be generated to choose which color is going to be digitized and receives the TR pulse These signals can be as simple as the output of a two bit counter that counts from 0 to 2 (0 1 2 0 1 2 etc) This counter should be incremented after the end of the previous line and before the first transfer pulse of the next line Also since each color will need a different VGA gain the appro- priate VGA gain value for each color should be sent to the LM9801 during this time 72 Parallel Output CCD Three LM9801s Figure 14 uses three LM9801s to achieve a 75 Mpixelsec (25M RGB pixelssec) pixel rate The three LM9801s are synchronized by applying the same MCLK and SYNC sig- nals to all three devices One LM9801 provides the clock signals required for the CCD Since the coefficient data for all three LM9801s will be latched simultaneously on the ris- ing edge of CCLK the correction coefficient bus must either be at least 24 bits wide (8 correction coefficient bits by 3 LM9801s) or run at a 75 MHz rate and be latched into a buffer between the correction coefficient databus and each LM9801 Similarly the output data for all three LM9801s will be available simultaneously at the 3 output databusses Since each LM9801 is dedicated to one color the VGA gain does not change during line scan TLH12814 – 41 FIGURE 14 Parallel Output CCD Three LM9801 http www nationalcom 28 |
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