LM9801 datasheet(22/34 Pages) NSC

22 / 34 page

Applications Information (Continued)

of the CCD is AC coupled to the LM9801 through a DC

blocking capacitor CCLAMP (the CCD’s DOS output is not

used) The value of this capacitor is determined by the leak-

age current of the LM9801’s OS input and the output imped-

ance of the CCD The leakage through the OS input deter-

mines how quickly the capacitor value will drift from the

clamp value of REF OUTMID which then determines how

many pixels can be processed before the droop causes er-

rors in the conversion (g01V is the recommended limit)

The output impedance of the CCD determines how quickly

the capacitor can be charged to the clamp value during the

black reference period at the beginning of every line

The minimum clamp capacitor value is determined by the

maximum droop the LM9801 can tolerate while converting

one CCD line The following equation takes the maximum

leakage current into the OS input the maximum allowable

droop (100 mV) the number of pixels on the CCD and the

pixel conversion rate (fMCLK 8) and provides the minimum

clamp capacitor value

CCLAMP MIN e

leakage current (A)

max droop (V)

number of pixels

conversion rate (Hz)

For example if the OS input leakage current is 20 nA worst-

case the CCD has 2700 active pixels the conversion rate is

25 MHz (fMCLK e 20 MHz) and the max droop desired is

01V the minimum clamp capacitor value is

CCLAMP MIN e

20 nA

01V

2700

25 MHz

216 pF

The maximum size of the clamp capacitor is determined by

the amount of time available to charge it to the desired val-

ue during the optical black portion of the CCD output The

internal clamp is on for each pixel from the rising edge of

the SH ref pulse to the falling edge of the SH signal pulse

(see Diagrams 7 and 8) This time can be calculated using

the values stored in the Sample Signal and Sample Refer-

ence configuration registers and the MCLK frequency For

normal CCDs

tDARK(s) e

2 a SS–SR

2fMCLK(Hz)

And for evenodd CCDs

tDARK(s) e

18 a SS–SR

2fMCLK(Hz)

Where SS is the value in the Sample Signal Position register

(0 – 15) SR is the value in the Sample Reference Position

the amount of time (per pixel) that the clamp is on

The following equation takes the number of optical black

pixels the amount of time (per pixel) that the clamp is

closed the CCD’s output impedance and the desired accu-

racy of the final clamp voltage and provides the maximum

clamp capacitor value that allows the clamp capacitor to

settle to the desired accuracy within a single line

CCLAMP MAX e

In(accuracy)

ROUT(X)

tDARK(s)

In(accuracy)

Where n e the number of optical black pixels tDARK is the

amount of time (per pixel) that the clamp is on ROUT is the

output impedance of the CCD and accuracy is the ratio of

the worst-case initial capacitor voltage to the desired final

capacitor voltage For example if a CCD has 18 black refer-

ence pixels the output impedance of the CCD is 1500X the

LM9801 is configured to clamp for 300 ns the worst case

initial voltage across the capacitor is 10V and the desired

voltage after clamping is 01V (accuracy e 1001 e 100)

then

CCLAMP MAX e

1500X

300 ns

In(100)

514 pF

The final value for CCLAMP should be less than or equal to

CCLAMP MAX but no less than CCLAMP MIN A value of

470 pF will work in this example

In some cases depending primarily on the choice of CCD

CCLAMP

MAX

may

actually

less

than

the

CCLAMP MIN meaning that the capacitor cannot be charged

to its final voltage during the black pixels at the beginning of

a line and hold its voltage without drooping for the duration

of that line This is usually not a problem because in most

applications the CCD is clocked continuously as soon as

power is applied In this case a larger capacitor can be

used (guaranteeing that the CCLAMP MIN requirement is

met) and the final clamp voltage is forced across the ca-

pacitor over multiple lines This equation calculates how

many lines are required before the capacitor settles to the

desired accuracy

lines e

ROUTnCCLAMP

tDARK

J In InitialVoltage

Final Voltage

Using the values shown before and a clamp capacitor value

of 001 mF this works out to be

lines e

1500X

001 mF

300 ns

J In 10V

01V

J e128lines

At a 25 MHz conversion rate this is about 14 ms

In this example a 001 mF capacitor takes 14 ms after pow-

er-up to charge to its final value but its droop across all

subsequent lines is now less than 2 mV (using the previous

example’s values) This wide margin is the reason a CCLAMP

value of 001 mF will work in most applications

43 VGA

The LM9801 has a VGA (Variable Gain Amplifier) that can

be used to increase the amplitude of the CCD signal prior to

sampling correction and digitization The gain of the VGA is

0 dB to 9 dB and is determined by the codes in the 4-bit

VGA Gain register as given by the equation

GainVGA (dB) e

VGA code

955

This gain may be changed at the line rate (not the pixel rate)

by writing to the configuration register You can write to the

configuration register to change the gain at any time but if

you write during a line the remaining pixels of that line may

be corrupted It is best to change the gain after all active

pixels have been read out or while SYNC is low

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