MP8869SGL datasheet(20/39 Pages) MPS

20 / 39 page

MP8869S

– 18V, 12A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP8869S Rev. 1.03

www.MonolithicPower.com

1/18/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP8869S UVLO comparator monitors the

input voltage, VIN, and output voltage of the

VCC regulator. The MP8869S is active when

the voltages exceed the UVLO rising threshold.

Soft-Start (SS) and Pre-Bias Start-Up

Soft start (SS) prevents the converter output

voltage

from

overshooting

during

start-up.

When the chip starts up, the internal circuitry

generates a soft-start voltage that ramps up

from 0V to VCC. When SS is lower than REF,

the error amplifier uses SS as the reference.

When SS is higher than REF, the error amplifier

uses REF as the reference.

The approximate typical soft-start time can be

calculated with Equation (2):

ref

V (V) C (nF)

t (ms)







(2)

Where Vref is reference voltage.

If the output of the MP8869S is pre-biased to a

certain voltage during start-up, the IC disables

the switching of both the HS-FET and LS-FET

until the voltage on the internal SS capacitor

exceeds the sensed output voltage at FB.

The MP8869S also provides a selectable soft-

stop

function

which

defines

the

output

discharge behavior after an EN shutdown. By

default, the output is not controlled after EN

shutdown. If setting the soft-stop control bit D[3]

to 1 in register 02 via the I2C, the output is

discharged linearly to zero in a quarter of the

soft-start time.

Over-Current Protection (OCP)

The MP8869S has a default, hiccup, cycle-by-

cycle, over-current limiting control. The current-

limit circuit employs both a high-side current

limit and a low-side valley current-sensing

algorithm. The MP8869S uses the RDS(ON) of the

LS-FET as a current-sensing element for the

valley current limit. If the magnitude of the high-

side current-sense signal is above the current-

limit threshold, the PWM on pulse is terminated,

and the LS-FET is turned on. Afterward, the

inductor current is monitored by the voltage

between GND and SW. GND is used as the

positive current sensing node, so GND should

be connected to the source terminal of the

bottom MOSFET. PWM is not allowed to initiate

a new cycle before the inductor current falls to

the valley threshold.

After

the

cycle-by-cycle

over-current

limit

occurs, the output voltage drops until VOUT is

below

the

under-voltage

(UV)

threshold

(typically 60% below the reference). Once UV is

triggered, the MP8869S enters hiccup mode to

restart the part periodically. This protection

mode is especially useful when the output is

dead shorted to ground. The average short-

circuit current is reduced greatly to alleviate

thermal issues and protect the regulator. The

MP8869S exits hiccup mode once the over-

current condition is removed.

Short the output to ground first, and then power

on the part. The MP8869S

’s I2C is disabled in

this condition. The I2C resumes operation after

the short circuit is removed. When the hiccup

over-current

protection

(OCP)

bit

D[1]

occurs if OCP is triggered, and FB under-

voltage protection (UVP) is triggered.

Power Good (PG)

The power good (PG) pin indicates whether the

output voltage is in the normal range compared

to the internal reference voltage. PG is an

open-drain structure. An external pull-up supply

is required. During power-up, the PG output is

pulled low. This indicates to the system to

remain off and keep the load on the output to a

minimum. This helps reduce in-rush current at

start-up.

When the output voltage is higher than 90%

and lower than 115% of the internal reference

voltage, and the soft start is finished, then the

PG signal is pulled high. When the output

voltage is lower than 85% after the soft start

finishes, the PG signal remains low. When the

output voltage is higher than 115% of the

internal reference, PG is switched low. The PG

signal rises back to high after the output voltage

drops below 105% of the internal reference

voltage.

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