MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP8719 Rev. 1.01

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13

8/3/2017

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chip divider. A minimum 0.22μF ceramic

capacitor must be connected close to the

VTTREF terminal for stable operation.

VTT responds quickly to track VTTREF with

±30mV in all conditions. The current capability

of the VTT regulator is up to 1A for both sink

and source modes. A minimum 22μF ceramic

capacitor must be connected close to the VTT

terminal. VTTS should be connected to the

positive node of the remote VTT output

capacitor as a separate trace from the high-

current line to VTT.

Configuring the EN Control

The MP8719 has two enable pins to turn the

internal regulators on or off (EN1, EN2). When

EN1 and EN2 are high, VDDQ, VTTREF and

VTT are turned on. When EN1 is low and EN2

is high, VDDQ and VTTREF remain on while

VTT is turned off and left at a high-impedance

state (Hi-Z). The VTT output floats and does not

sink or source current in this state. When EN1

and EN2 are low, all of the regulators remain off

and discharge to GND through a soft

shutdown(see Table 1).

Table 1: EN1/EN2 Control

EN1

EN2

VDDQ VTTREF VTT

High

High

On

On

On

Low

High

On

On

Off (Hi-Z)

Low

Low

Off

Off

Off

High

Low

Off

Off

Off

Ultrasonic Mode (USM)

Ultrasonic mode (USM) is designed to keep the

switching

frequency

above

an

audible

frequency area during light-load or no-load

conditions. Once the part detects that both the

HS-FET and the LS-FET are off for about 32µs),

frequency is out of the audible range. To

minimum value, the output discharge function is

range. USM is selected by MODE.

MODE Selection

The MP8719 implements MODE for multiple

applications for USM and switching frequency

selection. USM and the switching frequency

can be selected by a different resistor on the

3V3 logic mode pin. There are four modes that

can be selected for normal application with

external

resistors

(see

Table

2).

It

is

recommended to use a 1% accuracy resistor.

Table 2: Mode Selection

State

USM

Fs

Resistor to GND

M1

No

700kHz

0Ω

M2

Yes

700kHz

90kΩ

M3

No

500kHz

150kΩ

M4

Yes

500kHz

>230kΩ or float

VDDQ Power Good (PG)

The MP8719 uses a power good (PG) output to

indicate whether the output voltage of the

VDDQ regulator is ready. PG is the open drain

another voltage source through a resistor (e.g.:

100kΩ). After the input voltage is applied, the

MOSFET is turned on, so PG is pulled to GND

pulled low.

Soft Start (SS)

The

MP8719

employs

a

soft-start

(SS)

mechanism to ensure a smooth output during

power-up. When EN becomes high, the internal

reference voltage ramps up gradually, and the

output voltage ramps up smoothly as well.

Once the reference voltage reaches the target

value, the soft start finishes, and the MP8719

enters steady-state operation (see Figure 7).

Figure 7: Start-Up Power Sequence