MP8719 – 26V, 12A, HIGH-CURRENT, SYNC BUCK CONVERTER WITH ±1A LDO

MP8719 Rev1.01

www.MonolithicPower.com

12

8/3/2017

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© 2017 MPS. All Rights Reserved.

As the output current increases from light-load

condition, the current modulation regulation

time period becomes shorter. The HS-FET is

turned

on

more

frequently,

making

the

switching frequency increase. The output

current reaches the critical level when the

current modulator time is zero. The critical level

of the output current is determined with

Equation (1):

IN

S

OUT

OUT

IN

Critical

_

OUT

V

F

L

V

)

V

V

(

I













2

(1)

The MP8719 enters PWM mode once the

output current exceeds the critical level.

Afterward, the switching frequency remains

fairly constant over the output current range.

Jitter and FB Ramp

Jitter occurs in both PWM and skip mode when

HS-FET driver (see Figure 4 and Figure 5).

Jitter affects system stability, with noise

downward slope, so the jitter in DCM is usually

does not affect noise immunity directly.

V

RE F

V

FB

HS D river

J itter

V

S L O PE1

Figure 4: Jitter in PWM Mode

V

FB

HS D river

Jitter

V

REF

V

SL O P E 2

Figure 5: Jitter in Skip Mode

Operating

without

External

Ramp

Compensation

The

traditional

COT

control

scheme

is

intrinsically unstable if the output capacitor’s

ESR is not large enough to act as an effective

current-sense

resistor.

Usually,

ceramic

capacitors cannot be used directly as output

capacitors.

The

MP8719

has

built-in

internal

ramp

compensation to ensure that the system is

stable, even without the help of the output

capacitor’s ESR. Use the pure ceramic

capacitor solution, which reduces the output

ripple, total BOM cost, and board area

significantly.

Figure 6 shows a typical output circuit in PWM

mode without an external ramp circuit. Refer to

the Application Information section on page 16

for design steps without external compensation.

Figure 6: Simplified Output Circuit

When using a large capacitor (e.g.: OSCON) on

the output, add a >10µF ceramic capacitor in

parallel to minimize the effect of ESL.

Operating

with

External

Ramp

Compensation

Usually, the MP8719 is able to support ceramic

output capacitors without an external ramp.

However in some cases, the internal ramp may

not be enough to stabilize the system, or there

is too much jitter, which requires external ramp

compensation.

Refer

to

the

Application

Information section on page 16 for design steps

with external ramp compensation.

VTT and VTTREF

The MP8719 integrates high performance, low

dropout linear regulators (VTT and VTTREF) to

provide

complete

DDR3/DDR3L

power

solutions.

The

VTTREF

has

a

10mA

sink/source current capability and always tracks

half of VDDQ with ±1% accuracy using an on-