ACT8846 datasheet(30/44 Pages) ACTIVE-SEMI

30 / 44 page

ACT8846

Rev 7.0 06-Dec-2017

Innovative PowerTM

30 -

www.active-semi.com

ActivePMUTM is a trademark of Active-Semi.

I2CTM is a trademark of NXP.

nRSTO Output

nRSTO is an open-drain output which asserts low

upon startup or when manual reset is asserted via

the nPBIN input. When asserted on startup, nRSTO

remains low until reset time-out period expires.

When asserted due to manual-reset, nRSTO

immediately asserts low, then remains asserted low

until the nPBIN input is de-asserted and the reset

time-out period expires.

Connect a 10kΩ or greater pull-up resistor from

nRSTO to an appropriate voltage supply.

nIRQ Output

nIRQ is an open-drain output that asserts low any

time an interrupt is generated. Connect a 10kΩ or

greater pull-up resistor from nIRQ to an appropriate

voltage supply. nIRQ is typically used to drive the

interrupt input of the system processor.

Many of the ACT8846's functions support interrupt-

generation as a result of various conditions. These

are typically masked by default, but may be

unmasked via the I2C interface. For more

information about the available fault conditions,

refer to the appropriate sections of this datasheet.

Push-Button Control

The ACT8846 is designed to initiate a system

enable sequence when the nPBIN multi-function

input is asserted for 32ms. Once this occurs, a

power-on sequence commences, as described

below. The power-on sequence must complete and

the microprocessor must take control (by asserting

PWRHLD) before nPBIN is de-asserted. If the

microprocessor is unable to complete its power-up

routine successfully before the user releases the

push-button, the ACT8846 automatically shuts the

system down. This provides protection against

accidental or momentary assertions of the push-

button. If desired, longer “push-and-hold” times can

be implemented by simply adding an additional time

delay before asserting PWRHLD.

Control Sequences

The ACT8846 features a variety of control

sequences that are optimized for supporting system

enable and disable, as well as SLEEP mode of the

Rockchip RK31x8 processors.

Enabling/Disabling Sequence

A typical enable sequence is initiated whenever the

nPBIN is asserted low for 32ms via 50KΩ

resistance. The power control diagram is shown in

Figure

During

the

boot

sequence,

the

microprocessor must assert PWRHLD (GPIO6_B0)

to ensure that the system remains powered after

nPBIN is released. Once the power-up routine is

completed, the system remains enabled after the

push-button is released as long as PWRHLD is

asserted high. If the processor does not assert

PWRHLD before the user releases the push-button,

the boot-up sequence is terminated and all

regulators are disabled. This provides protection

against "false-enable", when the push-button is

accidentally depressed, and also ensures that the

system remains enabled only if the processor

successfully completes the boot-up sequence.

As with the enable sequence, a typical disable

sequence is initiated when the user presses the

push-button, which interrupts the processor via the

nPBSTAT output. After system is turned on, the

processor may shut down the system by setting

OFFSYSCLR[ ] to 1 then setting OFFSYS[ ] to 1, or

by pulling PWRHLD to logic low. The user could

force shut down ACT8846 anytime by pressing the

power on push-button for 10 seconds even when

software crashes.

SLEEP Mode Sequence

The

ACT8846

supports

RK31x8

processor’s

SLEEP mode operation. Once a successful power-

up routine has been completed, SLEEP mode may

be initiated through a variety of software-controlled

mechanisms.

SLEEP mode is typically initiated when the user

presses the push-button during normal operation.

Pressing the push-button asserts the nPBIN input,

which

asserts

the

nPBSTAT

output,

which

interrupts the processor. In response to this

interrupt the processor should disable REG6,

REG7, REG8, REG9, REG10 and REG12 via I2C,

then

de-assert

PWREN(GPIO6_B1),

disabling

REG3. PWRHLD should remain asserted during

SLEEP mode so that REG1, REG2, REG4, REG5,

and REG11 remain enabled.

The ACT8846 wakes up from SLEEP mode when

either the push-button and/or PWREN (GPIO6_B1)

is asserted. In either case, REG3 is enable which

allow the system to resume normal operation.



: Only for ACT8846QM468.

ACT8846 датащи(PDF) 30 Page - Active-Semi, Inc

ACT8846 датащи(HTML) 30 Page - Active-Semi, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL